MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 405
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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18.7.2 SPI Control Register 2
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
A
B
C
D
1. Slave output is enabled if SPIDDR bit 0 = 1, SS = 0, and MSTR = 0 (A, C).
2. Master output is enabled if SPIDDR bit 1 = 1 and MSTR = 1 (B, D).
3. SCK output is enabled if SPIDDR bit 2 = 1 and MSTR = 1 (B, D).
4. SS output is enabled if SPIDDR bit 3 = 1, SPICR1 bit 1 (SSOE) = 1, and MSTR = 1 (B, D). MODF input is enabled if SPI
5. GP = General-purpose
Normal
Bidirectional
DDR bit 3 = 0 and SSOE = 0. GP input is enabled if SPI DDR bit 3 = 0 and SSOE = 1.
Pin Mode
SPC0 MSTR
0
1
Address: 0x00cb_0001
0
1
0
1
Reset:
Read: Anytime
Write: Anytime; writing to unimplemented bits has no effect
SPISDOZ — SPI Stop in Doze Bit
SPC0 — Serial Pin Control Bit 0
Read:
Write:
Table 18-4. Bidirectional Pin Configurations
The SPIDOZ bit stops the SPI clocks when the CPU is in doze mode.
Reset clears SPISDOZ.
The SPC0 bit enables the bidirectional pin configurations shown in
Table
Freescale Semiconductor, Inc.
Slave data
output
Master data input
Slave data I/O
GP I/O
For More Information On This Product,
1 = SPI inactive in doze mode
0 = SPI active in doze mode
MISO Pin
Serial Peripheral Interface Module (SPI)
Bit 7
0
0
18-4. Reset clears SPC0.
Figure 18-3. SPI Control Register 2 (SPICR2)
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
(1)
6
0
0
Slave data input SCK input
Master data
output
GP
Master data I/O SCK output
MOSI Pin
(5)
I/O
5
0
0
(2)
SCK output
SCK input
4
0
0
SCK Pin
Serial Peripheral Interface Module (SPI)
(3)
3
0
0
Slave-select input
MODF/GP input (DDRSP3 = 0)
or GP output (DDRSP3 = 1)
Slave-select input
MODF/GP input (DDRSP3 = 0)
or GP output (DDRSP3 = 1)
Memory Map and Registers
2
0
1
SS Pin
Advance Information
SPISDOZ
1
0
(4)
SPC0
Bit 0
0
405
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