MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 572

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
22.7 Bypass Register
22.8 Boundary Scan Register
22.9 Restrictions
Advance Information
572
An IEEE 1149.1 standard-compliant Bypass Register is included. This
register which creates a single bit shift register path from TDI to the
Bypass Register to TDO when the BYPASS instruction is selected.
An IEEE 1149.1 standard-compliant Boundary Scan Register is
included. The Boundary Scan Register is connected between TDI and
TDO when the EXTEST or SAMPLE/PRELOAD instructions are
selected. This register captures signal pin data on the input pins, forces
fixed values on the output signal pins, and selects the direction and drive
characteristics (a logic value or high impedance) of the bidirectional and
three-state signal pins.
The test logic is implemented using static logic design, and TCLK can be
stopped in either a high or low state without loss of data. The system
logic, however, operates on a different system clock which is not
synchronized to TCLK internally. Any mixed operation requiring the use
of the IEEE 1149.1 standard test logic, in conjunction with system
functional logic that uses both clocks, must have coordination and
synchronization of these clocks done externally.
The control afforded by the output enable signals using the boundary
scan register and the EXTEST instruction requires a compatible
circuit-board test environment to avoid device-destructive
configurations. The user must avoid situations in which the output
drivers are enabled into actively driven networks.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
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