MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 238
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Second Generation FLASH for M•CORE (SGFM)
10.8.5 Master Mode
10.8.6 Emulation Mode
10.8.7 Debug Mode
10.9 FLASH Security Operation
Advance Information
238
NOTE:
If the MCU is booted in master mode with an external memory selected
as the boot device, the SGFM will not respond to the first transfer request
out of reset, even if the MLB address is equal to an address within the
SGFM array. This will allow the external boot device to provide the reset
vector and terminate the bus cycle.
In emulation mode, the SGFM module will not terminate the bus cycles
by asserting TA or TEA in response to array read requests. External
memory that emulates the FLASH will drive the data bus and the EBI
emulation chip mechanism will terminate the bus cycle instead of the
SGFM module.
In emulation mode, write accesses to the SGFM array will generate an
SGFM access error and set the ACCERR bit.
In debug mode, the SGFM module behaves exactly as it does in user
mode, except that the LOCK bit in SGFMMCR and the SGFMCLKD[6:0]
register bits are always writable.
The SGFM array provides security information to the integration module
and the rest of the MCU. A word in the FLASH configuration field stores
this information. This word is read automatically after each reset and is
stored in the SGFMSEC register.
In user mode, security can be bypassed via a back door access scheme
using an 8-byte long key. Upon successful completion of the back door
access sequence, the module output signal and status bit indicating that
the chip is secure are cleared.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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