MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 204

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Second Generation FLASH for M•CORE (SGFM)
10.2 Introduction
Advance Information
204
10.8.3
10.8.3.1
10.8.3.2
10.8.3.3
10.8.3.4
10.8.4
10.8.5
10.8.6
10.8.7
10.9
10.9.1
10.9.2
10.10 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
10.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
The second generation FLASH for M•CORE (SGFM) is constructed with
building blocks of 32,768 by 16 bits that can be used to generate 128-,
256-, 384- and 512-Kbyte electrically erasable and programmable
read-only memory arrays using two, four, six, and eight blocks
respectively. The SGFM is ideal for program and data storage for
single-chip applications and allows for field reprogramming without
external high-voltage sources.
The voltages required to program and erase the FLASH is generated
internally by on-chip charge pumps. Program and erase operations are
performed under CPU control through a command driven interface to an
internal state machine. All FLASH physical blocks can be programmed
or erased at the same time; however, it is not possible to read from a
FLASH physical block while the same block is being programmed or
erased. For 256-Kbyte and larger arrays, it is possible to program or
erase one pair of FLASH physical blocks under the control of software
routines executing out of another pair.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
FLASH Security Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Program and Erase Operations . . . . . . . . . . . . . . . . . . . . . 231
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Back Door Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Erase Verify Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Setting the SGFMCLKD Register. . . . . . . . . . . . . . . . . . 231
Program, Erase, and Verify Sequences. . . . . . . . . . . . . 232
FLASH User Mode Valid Commands. . . . . . . . . . . . . . . 234
FLASH User Mode Illegal Operations . . . . . . . . . . . . . . 236
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