MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 442
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
19.8.5 Control Registers
19.8.5.1 QADC Control Register 0 (QACR0)
Advance Information
442
Address: 0x00ca_000a and 0x00ca_000b
Reset:
Reset:
Read:
Read:
Write:
Write:
This subsection describes the QADC control registers.
QADC Control Register 0 (QACR0) establishes the QADC sampling
clock (QCLK) with prescaler parameter fields and defines whether
external multiplexing is enabled. Typically, these bits are written once
when the QADC is initialized and not changed thereafter.
Read: Anytime
Write: Anytime except during stop mode
MUX — Externally Multiplexed Mode Bit
The MUX bit configures the QADC for operation in externally
multiplexed mode, which affects the interpretation of the channel
numbers and forces the MA[1:0] pins to be outputs.
Freescale Semiconductor, Inc.
Figure 19-8. QADC Control Register 0 (QACR0)
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Externally multiplexed, up to 18 possible channels
0 = Internally multiplexed, up to 8 possible channels
Bit 15
MUX
Bit 7
0
0
0
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
QPR6
14
0
0
6
0
QPR5
13
0
0
5
0
QPR4
TRG
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
12
0
4
1
QPR3
11
0
0
3
0
QPR2
10
0
0
2
0
QPR1
9
0
0
1
1
MOTOROLA
QPR0
Bit 8
Bit 0
0
0
1
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