MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 324

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MMC2114CFCAG33

Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheets

Specifications of MMC2114CFCAG33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Timer Modules (TIM1 and TIM2)
16.7.1 Timer Input Capture/Output Compare Select Register
Advance Information
324
0x00ce_0017
0x00ce_0018
0x00ce_0019
0x00ce_001a
0x00ce_001b
0x00ce_001d
0x00ce_001e
1. S = CPU supervisor mode access only.
2. Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.
0x00ce_001c
0x00ce_001f
TIM1
Address
0x00cf_0017
0x00cf_0018
0x00cf_0019
0x00cf_001a
0x00cf_001b
0x00cf_001c
0x00cf_001d
0x00cf_001e
0x00cf_001f
TIM2
Table 16-2. Timer Modules Memory Map (Continued)
Address: TIM1 — 0x00ce_0000
Reset:
Read: Anytime; always read $00
Write: Anytime
IOS[3:0] — I/O Select Bits
Read:
Write:
The IOS[3:0] bits enable input capture or output compare operation
for the corresponding timer channels.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Output compare enabled
0 = Input capture enabled
TIM2 — 0x00cf_0000
Figure 16-2. Timer Input Capture/Output Compare
Bit 7
0
0
Pulse Accumulator Counter Register High (TIMPACNTH)
Pulse Accumulator Counter Register Low (TIMPACNTL)
Timer Modules (TIM1 and TIM2)
Pulse Accumulator Control Register (TIMPACTL)
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Pulse Accumulator Flag Register (TIMPAFLG)
Timer Port Data Direction Register (TIMDDR)
= Writes have no effect and the access terminates without a transfer error exception.
Timer Channel 3 Register Low (TIMC3L)
6
0
0
Timer Port Data Register (TIMPORT)
Timer Test Register (TIMTST)
Select Register (TIMIOS)
5
0
0
Reserved
Bits 7–0
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
4
0
0
(2)
IOS3
3
0
IOS2
2
0
IOS1
1
0
MOTOROLA
Access
²
IOS0
S
S
S
S
S
S
S
Bit 0
S
0
(1)

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