MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 481

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.10.1.2 Queue Priority Schemes
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
Because there are two conversion command queues and only one A/D
converter, a priority scheme determines which conversion occurs. Each
queue has a variety of trigger events that are intended to initiate
conversions, and they can occur asynchronously in relation to each
other and other conversions in progress. For example, a queue can be
idle awaiting a trigger event; a trigger event can have occurred, but the
first conversion has not started; a conversion can be in progress; a
pause condition can exist awaiting another trigger event to continue the
queue; and so on.
The following paragraphs and figures outline the prioritizing criteria used
to determine which conversion occurs in each overlap situation.
Each situation in
through S19. In each diagram, time is shown increasing from left to right.
The execution of queue 1 and queue 2 (Q1 and Q2) is shown as a string
of rectangles representing the execution time of each CCW in the queue.
In most of the situations, there are four CCWs (labeled C1 to C4) in both
queue 1 and queue 2. In some of the situations, CCW C2 is presumed
to have the pause bit set, to show the similarities of pause and
end-of-queue as terminations of queue execution.
Trigger events are described in
When a trigger event causes a CCW execution in progress to be
aborted, the aborted conversion is shown as a ragged end of a
shortened CCW rectangle.
Trigger
Freescale Semiconductor, Inc.
T1
T2
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Events that trigger queue 1 execution (external trigger, software-initiated
Events that trigger queue 2 execution (external trigger, software-initiated
single-scan enable bit, or completion of the previous continuous loop)
single-scan enable bit, timer period/interval expired, or completion of the
previous continuous loop)
Go to: www.freescale.com
Figure 19-23
Table 19-12. Trigger Events
through
Table
Queued Analog-to-Digital Converter (QADC)
Events
19-12.
Figure 19-33
is labeled S1
Advance Information
Digital Control
481