TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 93

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

<bit17:0>
(Note) For descriptions of interrupts and interrupt numbers, see Section 8.5.1.4 List of
8.6.2.8
<CLRENA>
Interrupt Sources.
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Interrupt Clear-Enable Register 2
Interrupt
number 39
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 47
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Use these bits to disable or determine which interrupts are currently disabled.
Writing “1” to a bit in this register disables the corresponding interrupt. Writing “0”
has no effect.
Reading a bit in this register returns the current state of the corresponding interrupt
as shown below.
0 = Disabled
1 = Enabled
15
23
31
7
0
0
Interrupt
number 38
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 46
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
14
22
30
6
0
0
Under development
number 37
Interrupt
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 45
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
13
21
29
Page81
5
0
0
“0” is read.
R
0
Interrupt
number 36
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 44
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
12
20
28
4
0
0
“0” is read.
CLRENA
CLRENA
R/W
R/W
R
0
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 43
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 35
11
19
27
3
0
0
number 34
Interrupt
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 42
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
10
18
26
2
0
0
Interrupt
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 41
[Write]
1: Disable
[Read]
0: Disabled
Interrupt
number 49
[Write]
1: Disable
[Read]
0: Disabled
1:Enabled
number 33
1: Enabled
17
25
1
9
0
0
0
CLRENA
R/W
Interrupt
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 40
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
Interrupt
number 48
[Write]
1: Disable
[Read]
0: Disabled
1: Enabled
number 32
TMPM330
16
24
0
8
0
0
0