TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 300

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13 Consumer Electronics Control (CEC)
13.2.13 Receive Interrupt Status Register [CECRSTAT]
<CECRIWAV>:
<CECRIOR>:
<CECRIACK>:
<CECRIMIN>:
<CECRIMAX>:
<CECRISTA>:
<CECRIEND>:
(Note)
bit Symbol
Read/Write
After reset
Function
Writing to this bit is ignored.
Indicates a start bit is detected.
Indicates “0” is detected after the specified time to output ACK bit “0”.
already been set.
Indicates 1 byte of data reception is completed.
Indicates that waveform error is detected. The error occurs when waveform error
detection is enabled in CECRCR3 <CECWAVEN>.
Indicates the receive buffer receives next data before reading the data that had
Indicates one bit cycle is shorter than the minimum cycle error detection time
specified in CECRCR1<CECMIN>.
Indicates one bit cycle is longer than the maximum cycle error detection time
specified in CECRCR1<CECMAX>.
“0” is
read.
―
7
R
0
CECRIWA
Interrupt
flag
1:
Wave
form error
6
V
R
0
Under development
CECRIOR CECRIACK CECRIMIN CECRIMA
Interrupt
flag
1:
Receive
buffer
overrun
Page288
5
R
0
Interrupt
flag
1:
ACK
collision
4
R
0
Interrupt
flag
1:
Min. cycle
error
R
3
0
Interrupt
flag
1:
Max.
cycle
error
2
R
X
0
CECRISTA CECRIEN
Interrupt
flag
1:
Start bit
detection
1
R
0
TMPM330
Interrupt
flag
1:
Completio
n
byte data
reception
of
0
D
R
0
1