TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 282

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12 Serial Bus Interface (SBI)
<SIOS>
<SIOF>
<SEF>
SCK pin (output)
SI pin
INTSBIx interrupt request
SBIxDBR
8-bit transmit/receive mode
Set the control register to the transfer/receive mode. Then writing the transmit data to
SBIxDBR and setting SBIxCR1 <SIOS> to “1” enables transmission and reception. The
transmit data is output through the SO pin at the falling of the serial clock, and the received
data is taken in through the SI pin at the rising of the serial clock, with the least-significant bit
(LSB) first. Once the shift register is loaded with the 8-bit data, it transfers the received data
to SBIxDBR and the INTSBIx interrupt request is generated. The interrupt service program
reads the received data from the data buffer register and writes the next transmit data.
Because SBIxDBR is shared between transmit and receive operations, the received data
must be read before the next transmit data is written.
In the internal clock operation, the serial clock will be automatically in the wait state until the
received data is read and the next transmit data is written.
In the external clock mode, shift operations are executed in synchronization with the
external serial clock. Therefore, the received data must be read and the next transmit data
must be written before the next shift operation is started. The maximum data transfer rate
for the external clock operation varies depending on the maximum latency between when
the interrupt request is generated and when the transmit data is written.
At the beginning of transmission, the same value as in the last bit of the previously
transmitted data is output in a period from setting <SIOF> to “1” to the falling edge of SCK.
Transmission and reception can be terminated by clearing <SIOS> to “0” or setting
SBIxCR1 <SIOINH> to “1” in the INTSBIx interrupt service program. If <SIOS> is cleared,
transmission and reception continue until the received data is fully transferred to SBIxDBR.
The program checks SBIxSR <SIOF> to determine whether transmission and reception
have come to an end. <SIOF> is cleared to “0” at the end of transmission and reception. If
<SIOINH> is set, the transmission and reception are aborted immediately and <SIOF> is
cleared to “0.”
(Note) The contents of SBIxDBR will not be retained after the transfer mode is
changed. The ongoing transmission and reception must be completed by
clearing <SIOS> to “0” and the last received data must be read before the
transfer mode is changed.
Fig. 12-28 Receive Mode (Example: Internal Clock)
a
0
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1
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Under development
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Page270
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5
Read the received data
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6
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7
a
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0
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1
b
<SIOS> is cleared.
2
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Read the received data
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7
TMPM330
b