TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 84
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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8 Exceptions
8.5.2.6
(1)
(2)
Pushing during ISR
Clearing an interrupt source
describes what is recommended at the service routine programming and how the source is
cleared.
Cortex-M3 core automatically pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack. No
extra programming is required for them.
ISR is being executed. We recommend you to push the contents of general-purpose registers that
might be rewritten.
cleared with the CG Interrupt Request Clear (ICRCG) Register.
cleared at its source. Therefore, the interrupt source must be cleared. Clearing the interrupt source
automatically clears the interrupt request signal from the clock generator.
value in the ICRCG register. When an active edge occurs again, a new interrupt request will be
detected.
An ISR requires specific programming according to the application to be used. This section
An ISR normally pushes register contents to the stack and handles an interrupt as required. The
Push the contents of other registers if needed.
Interrupt requests with higher priority and exceptions such as NMI are accepted even when an
If an interrupt source is used for clearing a standby mode, each interrupt request must be
If an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is
If an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding
Interrupt Service Routine (ISR)
Under development
Page72
TMPM330
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