TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 452

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

19 ROM protection
block.
FLCS
0x4004_0520
19.3 Register
The flash control register shows the status of the flash memory operation and the protection of each
Bit 0: Ready/Busy flag bit
Bit [21:16]: Protection status bits
The RDY/BSY output is provided as a means to monitor the status of automatic operation.
This bit is a function bit for the CPU to monitor the function. When the flash memory is in
automatic operation, it outputs "0" to indicate that it is busy. When the automatic operation is
terminated, it returns to the ready state and outputs "1" to accept the next command. If the
automatic operation has failed, this bit maintains the "0" output. By applying a hardware reset,
it returns to "1."
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
Function
Function
Each of the protection bits (6 bits) represents the protection status of the corresponding
block. When a bit is set to "1," it indicates that the block corresponding to the bit is
protected. When the block is protected, data cannot be written to it.
31
23
15
7
-
-
-
-
“0” i s read
R
0
Table 19-2 Flash control register
Under development
30
22
14
6
-
-
-
-
Protection
0: disabled
for Block 5
(Note 2)
1:enabled
Page440
BLPRO5
(Note 3)
29
21
13
R
5
-
-
-
Protection
for Block 4
(Note 2)
0: disabled
1:enabled
BLPRO4
(Note 3)
“0” i s read
28
20
12
R
4
R
0
-
-
-
“0” i s read
“0” i s read
R
R
0
0
Protection
for Block 3
0: disabled
1:enabled
BLPRO3
(Note 3)
27
19
11
R
3
-
-
-
Protection
for Block 2
0: disabled
1:enabled
BLPRO2
(Note 3)
26
18
10
R
2
-
-
-
Protection
for Block 1
0: disabled
1:enabled
BLPRO1
(Note 3)
25
17
R
9
1
-
-
-
TMPM330
Protection
for Block 0
0: disabled
1:enabled
1:Auto
operation
terminated
0:Auto
operating
Ready/Bus
y (Note 1)
RDY/BSY
BLPRO0
(Note 3)
24
16
R
8
0
R
1
-
-