TMPM330FWFG Toshiba, TMPM330FWFG Datasheet
TMPM330FWFG
Specifications of TMPM330FWFG
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TMPM330FWFG Summary of contents
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Bit RISC Microcontroller TX03 Series TMPM330FDFG/FYFG/FWFG ...
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... TOSHIBA CORPORATION All Rights Reserved ...
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ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* TMPM330FDFG/FYFG/FWFG R ...
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Introduction: Notes on the description of SFR (Special Function Register) under this specifica- tion An SFR (Special Function Register control register for periperal circuits (IP). The SFR addressses of IPs are described in the chapter on memory map, ...
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SAMCR(Control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol MODE After reset ...
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TMPM330FDFG/FYFG/FWFG ...
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Date Revision 2010/4/26 1 2010/10/6 2 Revision History Comment First Release Contents Revised ...
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...
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Table of Contents Introduction: Notes on the description of SFR (Special Function Register) under this specification TMPM330FDFG/FYFG/FWFG 1.1 Features......................................................................................................................................1 1.2 Block Diagram...........................................................................................................................4 1.3 Pin Layout (Top view)...............................................................................................................5 1.4 Pin names and Functions...........................................................................................................6 1.4.1 Sorted by Pin........................................................................................................................................................................6 1.4.2 Sorted by Port....................................................................................................................................................................12 ...
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... Memory map............................................................................................................................27 4.1.1 Memory map of the TMPM330FDFG...............................................................................................................................28 4.1.2 Memory Map of TMPM330FYFG....................................................................................................................................29 4.1.3 Memory Map of TMPM330FWFG...................................................................................................................................30 4.2 SFR area detail.........................................................................................................................31 5. Reset 5.1 Cold reset.................................................................................................................................33 5.2 Warm reset...............................................................................................................................34 5.2.1 Reset period.......................................................................................................................................................................34 5.2.2 After reset..........................................................................................................................................................................34 6. Clock/Mode control 6.1 Features....................................................................................................................................35 6.2 Registers..................................................................................................................................36 6 ...
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Exception Request and Detection 7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine (Pre-emption) 7.1.2.3 Executing an ISR 7.1.2.4 Exception exit 7.2 Reset Exceptions......................................................................................................................63 7.3 Non-Maskable Interrupts (NMI)..............................................................................................64 7.4 SysTick....................................................................................................................................64 7.5 Interrupts..................................................................................................................................65 7.5.1 Interrupt Sources................................................................................................................................................................65 7.5.1.1 Interrupt Route ...
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Port B Circuit Type 8.2.2.2 Port B Register 8.2.2.3 PBDATA (Port B data register) 8.2.2.4 PBCR (Port B output control register) 8.2.2.5 PBFR1 (Port B function register 1) 8.2.2.6 PBPUP (Port B pull-up control register) 8.2.2.7 PBIE (Port B ...
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PKDATA(Port K data register) 8.2.11.4 PKCR (Port K output control register) 8.2.11.5 PKFR1(Port K function register 1) 8.2.11.6 PKFR2(Port K function register 2) 8.2.11.7 PKPUP (Port K pull-up control register) 8.2.11.8 PKIE (Port K input control register) 8.3 Block ...
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Capture registers (TBxCP0, TBxCP1).............................................................................................................................203 9.5.6 Up-counter capture register (TBxUC).............................................................................................................................203 9.5.7 Comparators (CP0, CP1).................................................................................................................................................203 9.5.8 Timer Flip-flop (TBxFF0)...............................................................................................................................................203 9.5.9 Capture interrupt (INTCAPx0, INTCAPx1)...................................................................................................................203 9.6 Description of Operations for Each Mode.............................................................................204 9.6.1 16-bit Interval Timer Mode.............................................................................................................................................204 9.6.2 16-bit Event Counter Mode.............................................................................................................................................204 ...
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Receive Operation........................................................................................................................................................244 10.11.3.1 Receive Buffer 10.11.3.2 Receive FIFO Operation 10.11.3.3 I/O interface mode with SCLK output 10.11.3.4 Read Received Data 10.11.3.5 Wake-up Function 10.11.3.6 Overrun Error 10.12 Transmission......................................................................................................................248 10.12.1 Transmission Counter..................................................................................................................................................248 10.12.2 Transmission Control...................................................................................................................................................248 10.12.2.1 I/O Interface Mode 10.12.2.2 ...
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Interrupt Service Request and Release..........................................................................................................................285 11.5.10 Arbitration Lost Detection Monitor.............................................................................................................................285 11.5.11 Slave Address Match Detection Monitor.....................................................................................................................287 11.5.12 General-call Detection Monitor...................................................................................................................................287 11.5.13 Last Received Bit Monitor...........................................................................................................................................287 11.5.14 Data Buffer Register (SBIxDBR)................................................................................................................................287 11.5.15 Baud Rate Register (SBIxBR0)...................................................................................................................................287 11.5.16 Software Reset.............................................................................................................................................................287 11.6 ...
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Details of reception error 12.4.2.6 Stopping Reception 12.4.3 Transmission..................................................................................................................................................................340 12.4.3.1 Basic Operation 12.4.3.2 Preconfiguration 12.4.3.3 Detecting Transmission Error 12.4.3.4 Details of Transmission Error 12.4.3.5 Stopping Transmission 12.4.3.6 Retransmission 12.4.4 Software Reset...............................................................................................................................................................345 13. Remote control signal preprocessor (RMC) 13.1 Basic ...
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ADCMP0 (AD Conversion Result Comparison Register 0).......................................................................................389 14.3.20 ADCMP1 (AD Conversion Result Comparison Register 1).......................................................................................389 14.4 Description of Operations....................................................................................................390 14.4.1 Analog Reference Voltage.............................................................................................................................................390 14.4.2 AD Conversion Mode....................................................................................................................................................390 14.4.2.1 Normal AD conversion 14.4.2.2 Top-priority AD conversion 14.4.3 AD Monitor Function....................................................................................................................................................391 ...
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Alarm function.....................................................................................................................420 16.5.1 "Low" pulse (when the alarm register corresponds with the clock).............................................................................420 16.5.2 1Hz cycle "Low" pulse1 Hz...........................................................................................................................................421 16.5.3 16Hz cycle "Low" pulse16 Hz.......................................................................................................................................421 17. Flash Memory Operation 17.1 Flash Memory......................................................................................................................423 17.1.1 Features..........................................................................................................................................................................423 17.1.2 Block Diagram of the ...
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... Absolute Maximum Ratings................................................................................................485 19.2 DC Electrical Characteristics (1/3)......................................................................................486 19.3 DC Electrical Characteristics (2/3)......................................................................................487 19.4 DC Electrical Characteristics (3/3)......................................................................................488 19.4.1 TMPM330FDFG/TMPM330FYFG..............................................................................................................................488 19.4.2 TMPM330FWFG...........................................................................................................................................................488 19.5 10-bit ADC Electrical Characteristics.................................................................................489 19.6 AC Electrical Characteristics...............................................................................................490 19.6.1 AC measurement condition...........................................................................................................................................490 19.6.2 Serial Channel (SIO/UART)..........................................................................................................................................490 19 ...
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... Calendar (month, week, date and leap year) ROM RAM (FLASH) 512 Kbyte 32 Kbyte 256 Kbyte 16 Kbyte LQFP100-P-1414-0.50H 128 Kbyte 8 Kbyte On chip Flash Product name On chip RAM ROM TMPM330FDFG 512 Kbyte 32 Kbyte TMPM330FYFG 256 Kbyte 16 Kbyte TMPM330FWFG 128 Kbyte 8 Kbyte Page 1 TMPM330FDFG/FYFG/FWFG Package ...
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Features ・ Time correction + or − 30seconds (by software) ・ Alarm (Alarm output) ・ Alarm interrupt 5. Watchdog timer (WDT): 1 channel Watchdog timer (WDT) generates a reset or a non-maskable interrupt (NMI). 6. General-purpose serial interface (SIO/UART): ...
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LQFP100-P-1414-0.50H (14mm × 14mm, 0.5mm pitch) TMPM330FDFG/FYFG/FWFG Page 3 ...
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Block Diagram 1.2 Block Diagram Figure 1-1 TMPM330FDFG/FYFG/FWFGBlock Diagram Cortex-M3 I-Code CPU D-Code Debug System NVIC Bus Bridge CG SIO/UART (3ch) I2C/SIO (3ch) CEC RMC (2ch) Page 4 TMPM330FDFG/FYFG/FWFG I/F FLASH I/F RAM I/F BOOTROM PORT ...
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... RXIN0/PE3 TEST4 90 AIN0/PC0 AIN1/PC1 AIN2/PC2 AIN3/PC3 TB5IN0/AIN4/PD0 95 TB5IN1/AIN5/PD1 TB6IN0/AIN6/PD2 TB6IN1/AIN7/PD3 AIN8/PD4 AIN9/PD5 100 Figure 1-2 Pin Layout (LQFP100 TMPM330FDFG TMPM330FYFG 40 TMPM330FWFG Top View 35 30 Page 5 TMPM330FDFG/FYFG/FWFG PK0/CEC PJ1/INT1 PI3/TB3OUT PB7 PF6/SCK1 PF5/SI1/SCL1 PF4/SO1/SDA1 PB6 PI2/TB2OUT PB5 PI1/TB1OUT PJ6/INT6 PI0/TB0OUT PB4 PH3/TB1IN1 ...
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Pin names and Functions 1.4 Pin names and Functions Table 1-1 and Table 1-2 sort the input and output pins of the TMPM330FDFG/FYFG/FWFG by pin or port. Each table includes alternate pin names and functions for multi-function pins. 1.4.1 ...
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Table 1-1 Pin Names and Functions Sorted by Pin (2/6) Input/ Pin Type Pin Name Out- No. put PF7 I/O Function 19 INT5 I PE0 I/O Function 20 TXD0 O PE1 I/O Function 21 RXD0 I PE2 I/O Function 22 ...
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Pin names and Functions Table 1-1 Pin Names and Functions Sorted by Pin (3/6) Pin Type Pin Name No. PH3 Function 36 TB1IN1 Function 37 PB4 PI0 Function 38 TB0OUT PJ6 Function 39 INT6 PI1 Function 40 TB1OUT Function ...
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Table 1-1 Pin Names and Functions Sorted by Pin (4/6) Input/ Pin Type Pin Name Out- No. put Function/ PA1 I/O 56 Debug TCK/SWCLK I Test 57 TEST3 − PJ7 I/O Function 58 INT7 I Function/ PB1 I/O 59 Debug ...
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Pin names and Functions Table 1-1 Pin Names and Functions Sorted by Pin (5/6) Pin Type Pin Name No. PI6 Function 79 TB4IN0 Function 80 NMI Control 81 MODE Function 82 RESET PI7 Function 83 TB4IN1 PH6 Function 84 ...
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Table 1-1 Pin Names and Functions Sorted by Pin (6/6) Input/ Pin Type Pin Name Out- No. put PD2 I Function 97 AIN6 I TB6IN0 I PD3 I Function 98 AIN7 I TB6IN1 I PD4 I Function 99 AIN8 I ...
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Pin names and Functions 1.4.2 Sorted by Port Table 1-2 Pin Names and Functions Sorted by Port (1/6) Pin PORT Type No. Function/ PORT A 55 Debug Function/ PORT A 56 Debug Function/ PORT A 64 Debug Function/ PORT ...
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Table 1-2 Pin Names and Functions Sorted by Port (2/6) Pin PORT Type Pin Name No. PD1 PORT D Function 96 AIN5 TB5IN1 PD2 PORT D Function 97 AIN6 TB6IN0 PD3 PORT D Function 98 AIN7 TB6IN1 PD4 PORT D ...
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Pin names and Functions Table 1-2 Pin Names and Functions Sorted by Port (3/6) Pin PORT Type No. PORT F Function 44 PORT F Function 45 PORT F Function 46 PORT F Function 19 PORT G Function 26 PORT ...
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Table 1-2 Pin Names and Functions Sorted by Port (4/6) Pin PORT Type Pin Name No. PH4 PORT H Function 9 TB2IN0 PH5 PORT H Function 10 TB2IN1 PH6 PORT H Function 84 TB3IN0 PH7 PORT H Function 85 TB3IN1 ...
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Pin names and Functions Table 1-2 Pin Names and Functions Sorted by Port (5/6) Pin PORT Type No. PORT K Function 50 PORT K Function 51 PORT K Function 7 - Function 82 - Function 80 - Control 81 ...
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Table 1-2 Pin Names and Functions Sorted by Port (6/6) Pin PORT Type Pin Name No DVDD3 - PS 73 DVSS - PS 75 RVSS - PS 76 RVDD3 Input/ Out- put − Power supply pin − ...
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Pin Numbers and Power Supply Pins 1.5 Pin Numbers and Power Supply Pins Table 1-3 Pin Numbers and Power Supplies Power supply DVDD3 AVDD3 RVDD3 Voltage range Pin No. PA,PB,PE,PF,PG,PH,PI,PJ,PK,X1,X2,XT1, 14, 62,71 XT2,RESET,NMI,MODE 2 Page ...
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... The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core. TMPM330FDFG/FYFG/FWFG has 50 interrupt inputs. The number of interrupt inputs is reflected in <IN- TLINESNUM[4:0]> bit of NVIC register. In this product, if read <INTLINESNUM[4:0]> bit, "0y00001" is read out. Product Name Core Revision TMPM330FDFG r1p1-00rel0 TMPM330FYFG TMPM330FWFG r1p1-01rel0 Configurable Options Implementation MPU Not implementable ETM Implementable Page 19 ...
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Exceptions/ Interruptions 2.3.2 Number of Priority Level Interrupt Bits The Cortex-M3 core can optionally configure the number of priority level interrupt bits from 3 bits to 8 bits. TMPM330FDFG/FYFG/FWFG has three priority level interrupt bits. The number of priority ...
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Events The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV instruction execution event is input, the core returns from low-power consumption mode caused by WFE in- struction. ...
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Exclusive access TMPM330FDFG/FYFG/FWFG Page 22 ...
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Debug Interface 3.1 Specification Overview TMPM330FDFG/FYFG/FWFG contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell™(ETM) unit for instruction trace output.Trace data is output to the dedicated pins(TRACEDATA[3:0], SWV) ...
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Pin Functions 3.4 Pin Functions The debug interface pins can also be used as general-purpose ports. The PA0 and PA1 pins are shared between the JTAG debug port function and the Serial Wire Debug Port function. The PB0 pin ...
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Table 3-2 Debug Interface Pins and Related Port Settings after Reset Port Name Debug Function (Bit Name) PA0 TMS/SWDIO PA1 TCK/SWCLK PB0 TDO/SWV PB1 TDI PB2 TRST PA2 TRACECLK PA3 TRACEDATA0 PA4 TRACEDATA1 PA5 TRACEDATA2 PA6 TRACEDATA3 − : Don’t ...
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Connection with a Debug Tool 3.7 Connection with a Debug Tool 3.7.1 About connection with debug tool Concerning a connection with debug tools, refer to manufactures recommendations. Debug interface pins contain a pull-up resistor and a pull-down resistor.When debug ...
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Memory Map 4.1 Memory map The memory maps for theTMPM330FDFG/FYFG/FWFG are based on the ARM Cortex-M3 processor core mem- ory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped ...
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Memory map 4.1.1 Memory map of the TMPM330FDFG Figure 4-1shows the memory map of the TMPM330FDFG. Vendor-Specific CPU Register Region Fault SFR Fault Internal RAM (32K) Fault Internal ROM (512K) Figure 4-1 Memory Map (TMPM330FDFG) Page 28 TMPM330FDFG/FYFG/FWFG ...
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Memory Map of TMPM330FYFG Figure 4-2 shows the memory map of the TMPM330FYFG. Figure 4-2 Memory Map (TMPM330FYFG) Note:In addition to 256KB flash area, the TMPM330FYFG provides 128-word data/ password area (1 page) for Show Product Information command in ...
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... Memory map 4.1.3 Memory Map of TMPM330FWFG Figure 4-3 shows the memory map of the TMPM330FWFG. Vencor-Specific CPU Register Region Fault SFR Fault Internal RAM (8K) Fault Internal ROM (128K) Figure 4-3 Memory Map (TMPM330FWFG) Page 30 TMPM330FDFG/FYFG/FWFG ...
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SFR area detail This section contains the list of addresses in the SFR area (0x4000_0000 through 0x4007_FFFF) assigned to pe- ripheral function. Access to the Reserved areas in the Table 4-1 is prohibited. As for the SFR area, reading ...
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SFR area detail TMPM330FDFG/FYFG/FWFG Page 32 ...
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Reset The TMPM330FDFG/FYFG/FWFG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting <SYSRESETREQ> in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the ...
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Warm reset 5.2 Warm reset 5.2.1 Reset period As a precondition, ensure that the power supply voltage is within the operating range and the internal high- frequency oscillator is providing stable oscillation. To reset the TMPM330FDFG/FYFG/FWFG, assert the RESET ...
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Clock/Mode control 6.1 Features The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL clock multi- plication circuit and oscillator. There is also the low power consumption mode which can reduce power consumption ...
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Registers 6.2 Registers 6.2.1 Register List The following table shows the CG-related registers and addresses. System control register Oscillation control register Standby control register PLL selection register System clock selection register Register name CGSYSCR CGOSCCR CGSTBYCR CGPLLSEL CGCKSEL Page ...
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CGSYSCR (System control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol - ...
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Registers 6.2.3 CGOSCCR (Oscillation control register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-14 ...
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CGSTBYCR (Standby control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol - ...
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Registers 6.2.5 CGPLLSEL (PLL Selection Register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-1 ...
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CGCKSEL (System clock selection register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Clock control 6.3 Clock control 6.3.1 Clock System Block Diagram Each clock is defined as follows: fosc fs fpll fc fgear fsys fperiph φT0 The high-speed clock fc and the prescaler clock ΦT0 are dividable as follows. High-speed clock ...
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Clock system Diagram Figure 6-1 shows the clock system diagram. CGOSCCR<WUEON> CGOSCCR<WUPT[2:0]> Warming-up timer CGOSCCR <WUPSEL> CGOSCCR <XEN> Starts oscillation after reset X1 High-spped oscillation X2 fosc CGOSCCR <PLLON> Stops after releasing reset XT1 Low-spped oscillation XT2 fs 1/32 ...
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Clock control 6.3.4 Clock Multiplication Circuit (PLL) This circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock (fosc result, the input frequency to oscillator can be low, and the internal clock be ...
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The following are the examples of the warm-up function configuration. <Example1> Securing the stability time for the PLL CGOSCCR<WUPSEL> = "0" : Specify the warm-up counter CGOSCCR<WUPT[2:0]> = "010" : Specify the warm-up time (204.8μs) CGOSCCR<WUEON> = "1" : Start ...
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Clock control 6.3.6 System Clock The TMPM330FDFG/FYFG/FWFG offers two selectable system clocks: low-speed or high-speed. The high- speed clock is dividable. Note 1: Switching of clock gear is executed when a value is written to the CGSYSCR<GEAR[2:0]> register. The ...
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System Clock Pin Output Function The TX03 enables to output the system clock from a pin. The PK1/SCOUT pin can output the low speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral ...
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Modes and Mode Transitions 6.4 Modes and Mode Transitions 6.4.1 Mode Transitions The NORMAL mode and the SLOW mode use the high-speed and low-speed clocks for the system clock respectively. The IDLE, SLEEP and STOP modes can be used ...
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Operation mode Two operation modes, NORMAL and SLOW, are available. The features of each mode are described in the fol- lowing section. 6.5.1 NORMAL mode This mode is to operate the CPU core and the peripheral hardware by using ...
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Low Power Consumption Modes 6.6 Low Power Consumption Modes The TX03 has three low power consumption modes: IDLE, SLEEP and STOP. To shift to the low power con- sumption mode, specify the mode in the system control register CGSTBYCR<STBY[2:0]> ...
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STOP mode All the internal circuits including the internal oscillator are brought to a stop in the STOP mode. By releasing the STOP mode, the device returns to the preceding mode of the STOP mode and starts operation. The ...
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Low Power Consumption Modes 6.6.5 Operational Status in Each Mode Table 6-7 show the operational status in each mode. For I/O port, "ο" and "×" indicate that input/output is enabled and disabled respectively. For other functions, "ο" and "×" ...
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Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request, Non-Maskable Interrupt (NMI) or reset. The release source that can be used is determined by the low power consumption mode selected. ...
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Low Power Consumption Modes 6.6.7 Warm-up Mode transition may require the warm-up so that the internal oscillator provides stable oscillation. In the mode transition from STOP to the NORMAL/ SLOW or from SLEEP to NORMAL, the warm-up counter is ...
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Clock Operations in Mode Transition The clock operations in mode transition are described in Chapter 6.6.8.1 to 6.6.8.4. 6.6.8.1 Transition of operation modes: NORMAL → STOP → NORMAL When returning to the NORMAL mode from the STOP mode, the ...
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Low Power Consumption Modes 6.6.8.3 Transition of operation modes: SLOW → STOP → SLOW The warm-up is activated automatically necessary to set the warm-up time before entering the STOP mode. Mode SLOW fs Warm-up fsys (System clock=fs) ...
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Exceptions This chapter describes features, types and handling of exceptions. Exceptions have close relation to the CPU core. Refer to "Cortex-M3 Technical Reference Manual" if needed. 7.1 Overview An exception causes the CPU to stop the currently executing process ...
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Overview 7.1.2 Handling Flowchart The following shows how an exception/interrupt is handled. In the following descriptions, Each step is described later in this chapter. Processing Detection by CG/CPU Handling by CPU Branch to ISR Execution of ISR Return from ...
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Exception detection If multiple exceptions occur simultaneously, the CPU takes the exception with the highest priority. Table 7-1 shows the priority of exceptions. "Configurable" means that you can assign a priority level to that exception. Memory Management, Bus Fault ...
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Overview Table 7-2 Priority grouping setting <PRIGROUP[2:0]> setting 000 001 010 011 100 101 110 111 Note:If the configuration of <PRI_n> is less than 8 bits, the lower bit is "0". For the example, in 7.1.2.2 Exception Handling and ...
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Old SP → SP → (2) Fetching an ISR The CPU enables instruction to fetch the interrupt processing with data store to the register. Prepare a vector table containing the top addresses of ISRs for each exception.After reset, the vector ...
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Overview 7.1.2.3 Executing an ISR An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the user. An ISR may need to include code for clearing the interrupt request so that the same interrupt will ...
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Reset Exceptions Reset exceptions are generated from the following three sources. Use the Reset Flag (CGRSTFLG) Register of the Clock Generator to identify the source of a reset. ・ External reset pin A reset exception occurs when an external ...
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Non-Maskable Interrupts (NMI) 7.3 Non-Maskable Interrupts (NMI) Non-maskable interrupts are generated from the following two sources. Use the NMI Flag (CGNMIFLG) Register of the clock generator to identify the source of a non-maskable interrupt. ・ External NMI pin A ...
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Interrupts This chapter describes routes, sources and required settings of interrupts. The CPU is notified of interrupt requests by the interrupt signal from each interrupt source. It sets priority on interrupts and handles an interrupt request with the highest ...
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Interrupts 7.5.1.2 Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC's Interrupt Set-Pending Register. ・ From external pin ・ From peripheral function ・ By setting ...
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List of Interrupt Sources Table 7-3 shows the list of interrupt sources. Table 7-3 List of Interrupt Sources No. Interrupt Source 0 INT0 Interrupt pin (PJ0/70pin) 1 INT1 Interrupt pin (PJ1/49pin) 2 INT2 Interrupt pin (PJ2/86pin) 3 INT3 Interrupt ...
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Interrupts Table 7-3 List of Interrupt Sources No. 40 INTTB7 41 INTTB8 42 INTTB9 43 INTCAP20 44 INTCAP21 45 INTCAP30 46 INTCAP31 47 INTCAP40 48 INTCAP41 49 INTAD 7.5.1.6 Active level The active level indicates which change in signal ...
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Interrupt Handling 7.5.2.1 Flowchart The following shows how an interrupt is handled. In the following descriptions, handling. Processing Set the relevant NVIC registers for detecting interrupts. Set the clock generator as well if each interrupt source is used to ...
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Interrupts Processing ISR execution Return to preceding program 7.5.2.2 Preparation When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any unexpected interrupt on the way. Initiating an interrupt or changing its ...
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Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but the number of bits actually used varies with each product.Priority level 0 is the highest priority level.If multiple sources have the same ...
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Interrupts Before enabling an interrupt, clear the corresponding interrupt request already held. This can avoid unexpected interrupt.To clear corresponding interrupt request, write a value corresponding to the in- terrupt to be used to the CGICRCG register.See "7.6.3.5 CGICRCG(CG Interrupt ...
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Detection by CPU The CPU detects an interrupt request with the highest priority. 7.5.2.5 CPU processing On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack then enter the ISR. ...
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Exception/Interrupt-Related Registers 7.6 Exception/Interrupt-Related Registers The CPU's NVIC registers and clock generator registers described in this chapter are shown below with their respective addresses. 7.6.1 Register List NVIC registers SysTick Control and Status Register SysTick Reload Value Register SysTick ...
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NVIC Registers 7.6.2.1 SysTick Control and Status Register 31 30 bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset ...
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Exception/Interrupt-Related Registers 7.6.2.2 SysTick Reload Value Register 31 bit symbol - After reset 0 23 bit symbol After reset 15 bit symbol After reset 7 bit symbol After reset Bit Bit Symbol Type 31-24 − R 23-0 RELOAD R/W ...
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SysTick Current Value Register 31 30 bit symbol - - After reset bit symbol After reset 15 14 bit symbol After reset 7 6 bit symbol After reset Bit Bit Symbol Type 31-24 − R ...
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Exception/Interrupt-Related Registers 7.6.2.4 SysTick Calibration Value Register 31 bit symbol NOREF After reset 0 23 bit symbol After reset 0 15 bit symbol After reset 0 7 bit symbol After reset 1 Bit Bit Symbol Type 31 NOREF R ...
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Interrupt Set-Enable Register SETENA SETENA bit symbol (Interrupt 31) (Interrupt 30) (Interrupt 29) After reset SETENA SETENA bit symbol (Interrupt 23 (Interrupt 22) (Interrupt 21) After reset SETENA ...
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Exception/Interrupt-Related Registers 7.6.2.6 Interrupt Set-Enable Register 2 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 SETENA bit symbol (Interrupt 47) After reset 0 7 SETENA bit symbol (Interrupt 39) After reset 0 ...
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Interrupt Clear-Enable Register CLRENA CLRENA bit symbol (Interrupt 31) (Interrupt 30) (Interrupt 29) After reset CLRENA CLRENA bit symbol (Interrupt 23) (Interrupt 22) (Interrupt 21) After reset CLRENA ...
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Exception/Interrupt-Related Registers 7.6.2.8 Interrupt Clear-Enable Register 2 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 CLRENA bit symbol (Interrupt 47) After reset 0 7 CLRENA bit symbol (Interrupt 39) After reset 0 ...
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Interrupt Set-Pending Register SETPEND SETPEND SETPEND bit symbol (Interrupt 31) (Interrupt 30) (Interrupt 29) After reset Undefined Undefined 23 22 SETPEND SETPEND SETPEND bit symbol (Interrupt 23) (Interrupt 22) (Interrupt 21) After reset Undefined Undefined 15 ...
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Exception/Interrupt-Related Registers 7.6.2.10 Interrupt Set-Pending Register 2 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 SETPEND bit symbol (Interrupt 47) After reset Undefined 7 SETPEND bit symbol (Interrupt 39) After reset Undefined ...
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Interrupt Clear-Pending Register CLRPEND CLRPEND CLRPEND bit symbol (Interrupt 31) (Interrupt 30) (Interrupt 29) After reset Undefined Undefined 23 22 CLRPEND CLRPEND CLRPEND bit symbol (Interrupt 23) (Interrupt 22) (Interrupt 21) After reset Undefined Undefined 15 ...
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Exception/Interrupt-Related Registers 7.6.2.12 Interrupt Clear-Pending Register 2 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 CLRPEND bit symbol (Interrupt 47) After reset Undefined 7 CLRPEND bit symbol (Interrupt 39) After reset Undefined ...
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Interrupt Priority Register Each interrupt is provided with eight bits of an Interrupt Priority Register. The following shows the addresses of the Interrupt Priority Registers corresponding to interrupt numbers. 31 0xE000_E400 PRI_3 0xE000_E404 PRI_7 0xE000_E408 PRI_11 0xE000_E40C PRI_15 0xE000_E410 ...
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Exception/Interrupt-Related Registers 7.6.2.14 Vector Table Offset Register 31 bit symbol - After reset 0 23 bit symbol After reset 0 15 bit symbol After reset 0 7 bit symbol TBLOFF After reset 0 Bit Bit Symbol Type 31-30 − ...
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Application Interrupt and Reset Control Register 31 30 bit symbol After reset bit symbol After reset bit symbol ENDIANESS - After reset bit symbol - - After ...
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Exception/Interrupt-Related Registers 7.6.2.16 System Handler Priority Register Each exception is provided with eight bits of a System Handler Priority Register. The following shows the addresses of the System Handler Priority Registers corresponding to each ex- ception. 0xE000_ED18 0xE000_ED1C 0xE000_ED20 ...
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System Handler Control and State Register 31 30 bit symbol - - After reset bit symbol - - After reset SVCALL BUSFAULT MEMFAULT bit symbol PENDED PENDED After reset 0 0 ...
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Exception/Interrupt-Related Registers Bit Bit Symbol Type 3 USGFAULT R/W ACT 2 − BUSFAULT R/W ACT 0 MEMFAULT R/W ACT Note:You must clear or set the active bits with extreme caution because clearing and setting these bits does ...
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Clock generator registers 7.6.3.1 CGIMCGA(CG Interrupt Mode Control Register bit symbol - After reset bit symbol - After reset bit symbol - After reset ...
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Exception/Interrupt-Related Registers Bit Bit Symbol Type 14-12 EMCG1[2:0] R/W 11-10 EMST1[1: − INT1EN R/W 7 − R 6-4 EMCG0[2:0] R/W 3-2 EMST0[1: − INT0EN R/W Note 1: <EMSTx> is effective only ...
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CGIMCGB(CG Interrupt Mode Control Register bit symbol - After reset bit symbol - After reset bit symbol - After reset bit symbol - After ...
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Exception/Interrupt-Related Registers Bit Bit Symbol Type 8 INT5EN R/W 7 − R 6-4 EMCG4[2:0] R/W 3-2 EMST4[1: − INT4EN R/W Note 1: <EMSTx> is effective only when <EMCGx[2:0]> is set to "100" for both rising ...
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CGIMCGC(CG Interrupt Mode Control Register bit symbol - After reset bit symbol - After reset bit symbol - After reset bit symbol - After ...
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Exception/Interrupt-Related Registers Bit Bit Symbol Type 11-10 EMST9[1: − INT9EN R/W 7 − R 6-4 EMCG8[2:0] R/W 3-2 EMST8[1: − INT8EN R/W Note 1: <EMSTx> is effective only when <EMCGx[2:0]> is ...
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CGIMCGD(CG Interrupt Mode Control Register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Exception/Interrupt-Related Registers 7.6.3.5 CGICRCG(CG Interrupt Request Clear Register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol ...
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CGNMIFLG(NMI Flag Register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - ...
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Exception/Interrupt-Related Registers 7.6.3.7 CGRSTFLG (Reset Flag Register) 31 bit symbol - After pin reset 0 23 bit symbol - After pin reset 0 15 bit symbol - After pin reset 0 7 bit symbol - After pin reset 0 ...
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Input/Output Ports 8.1 Port Functions 8.1.1 Function Lists TMPM330FDFG/FYFG/FWFG has 78 ports. Besides the ports function, these ports can be used as I/O pins for peripheral functions. Table 8-1, Table 8-2 and Table 8-3 show the port function table. ...
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Port Functions Table 8-2 Port Function List (Port D-Port G) Port Pin PD0 PD1 PD2 PD3 Port D PD4 PD5 PD6 PD7 PE0 PE1 PE2 Port E PE3 PE4 PE5 PE6 PF0 PF1 PF2 PF3 Port F PF4 PF5 ...
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Table 8-3 Port Function List (Port H-Port K) Pull-up Input/Out- Port Pin put Pull-down PH0 I/O Pull-up PH1 I/O Pull-up PH2 I/O Pull-up PH3 I/O Pull-up Port H PH4 I/O Pull-up PH5 I/O Pull-up PH6 I/O Pull-up PH7 I/O Pull-up ...
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Port Functions 8.1.2 Port Registers Outline The following registers need to be configured to use ports. ・ PxDATA: Port x data register To read/ write port data. ・ PxCR: Port x output control register To control output. PxIE needs ...
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Port States in STOP Mode Input and output in STOP mode are enabled/disabled by the CGSTBYCR<DRVE> bit. If PxIE or PxCR is enabled with <DRVE>=1, input or output is enabled respectively in STOP mode.If <DRVE>=0, both input and output ...
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Port functions 8.2 Port functions This chapter describes the port registers detail. This chapter describes only "circuit type" reading circuit configuration.For detailed circuit diagram, refer to "8.3 Block Diagrams of Ports". 8.2.1 Port A (PA0 to PA7) The port ...
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PADATA (Port A data register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.1.5 PAFR1 (Port A function register 1) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit ...
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PAPUP (Port A pull-up control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Port functions 8.2.1.8 PAIE (Port A input control register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PA7IE After reset 0 Bit Bit ...
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Port B (PB0 to PB7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port B performs the debug interface. ...
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Port functions 8.2.2.3 PBDATA (Port B data register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PB7 After reset 0 Bit Bit Symbol ...
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PBFR1 (Port B function register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Port functions 8.2.2.6 PBPUP (Port B pull-up control register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PB7UP After reset 0 Bit Bit ...
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Port C (PC0 to PC3) The port 4-bit input port. Besides the general-purpose input function, the port C functions as analog input pins of the AD converter. Reset initializes all bits of the port C as ...
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Port functions 8.2.3.3 PCDATA (Port C data register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol ...
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PCIE (Port C input control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Port functions 8.2.4 Port D (PD0 to PD7) The port 8-bit input port. Besides the general-purpose input function, the port D receives an analog input of the AD converter and a 16-bit timer input. Reset initializes ...
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PDDATA (Port D data register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.4.5 PDPUP (Port D pull-up control register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PD7UP After reset 0 Bit Bit ...
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Port E (PE0 to PE6) The port general-purpose, 7-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port E performs the serial interface ...
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Port functions 8.2.5.3 PEDATA (Port E data register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol ...
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PEFR1(Port E function register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.5.6 PEFR2(Port E function register 2) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol ...
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PEPUP (Port E pull-up control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Port functions 8.2.6 Port F (PF0 to PF7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port F performs ...
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PFDATA (Port F data register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.6.5 PFFR1(Port F function register 1) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PF7F1 After reset 0 Bit Bit Symbol ...
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PFFR2(Port F function register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.6.8 PFPUP (Port F pull-up control register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PF7UP After reset 0 Bit Bit ...
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Port G (PG0 to PG7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port G performs the functions of ...
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Port functions 8.2.7.3 PGDATA (Port G data register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PG7 After reset 0 Bit Bit Symbol ...
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PGFR1(Port G function register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.7.6 PGOD (Port G open drain control register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PG7OD After reset 0 Bit ...
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PGIE (Port G input control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Port functions 8.2.8 Port H (PH0 to PH7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port H performs ...
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PHDATA (Port H data register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.8.5 PHFR1(Port H function register 1) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PH7F1 After reset 0 Bit Bit Symbol ...
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PHPUP (Port H pull-up control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Port functions 8.2.9 Port I (PI0 to PI7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port I performs ...
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PIDATA(Port I data register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol PI7 ...
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Port functions 8.2.9.5 PIFR1(Port I function register 1) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PI7F1 After reset 0 Bit Bit Symbol ...
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PIPUP (Port I pull-up control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Port functions 8.2.10 Port J (PJ0 to PJ7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port J performs ...
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PJDATA (Port J data register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.10.5 PJFR1(Port J function register 1) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PJ7F1 After reset 0 Bit Bit Symbol ...
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PJPUP (Port J pull-up control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit ...
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Port functions 8.2.11 Port K (PK0 to PK2) The port general-purpose, 3-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port K performs ...
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PKDATA(Port K data register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol - ...
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Port functions 8.2.11.5 PKFR1(Port K function register 1) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol ...
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PKFR2(Port K function register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol ...
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Port functions 8.2.11.8 PKIE (Port K input control register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit ...
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Block Diagrams of Ports 8.3.1 Port Types The ports are classified as shown below. Please refer to the following pages for the block diagrams of each port type. Dot lines in the figure indicate the part of the equivalent ...
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Block Diagrams of Ports 8.3.2 Type T1 (Pull-up Control) (Output Controll) (Output Latch) (Input Control) Drive Disable in STOP Mode (Set by <DRVE>) PxPUP PxCR PxDATA PxIE 0 1 Port Read Figure 8-1 Port Type T1 Page 156 TMPM330FDFG/FYFG/FWFG ...
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Type T2 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable In STOP Mode Set by <DRVE> Figure 8-2 Port type T2 Page 157 TMPM330FDFG/FYFG/FWFG ...
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Block Diagrams of Ports 8.3.4 Type T3 (Function Control) Function Input Drive Disable in STOP Mode (Set by <DRVE>) PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 PxDATA (Output Latch) PxIE (Input Control Port Read Figure 8-3 Port ...
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Type T4 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open Drain Control) PxIE (Input Control) Port Read Function Input Drive Disable In STOP Mode Set by <DRVE> Figure 8-4 Port Type ...
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Block Diagrams of Ports 8.3.6 Type5 T5 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Function Input BOOT Drive Disable in STOP Mode (Set by <DRVE> Figure 8-5 Port Type ...
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Type T6 PxPDN (Pull-down Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable In STOP Mode (Set by <DRVE> Figure 8-6 Port Type T6 Page 161 TMPM330FDFG/FYFG/FWFG ...
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Block Diagrams of Ports 8.3.8 Type T7 Interrupt Input Drive Disable In STOP Mode (Set by <DRVE>) PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control Port Read Noise Filter ( ...
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Type T8 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Interrupt Noise Filter Input ( ) Drive Disable In STOP Mode Set by <DRVE> Figure ...
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Block Diagrams of Ports 8.3.10 Type T9 (Pull-up Control) (Output Control) (Function Control) (Output Latch) (Input Control) Port Read Drive Disable In STOP Mode (Set by <DRVE> PxPUP PxCR PxFR1 1 Function Output PxDATA 0 PxIE 0 1 Figure ...
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Type T10 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Drive Disable in STOP Mode (Set by <DRVE>) 1 Function Output Figure 8-10 Port ...
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Block Diagrams of Ports 8.3.12 Type T11 (Pull-up Control) (Output Control) (Function Control) (Output Latch) (Input Control) Port Read Drive Disable in STOP Mode (Set by <DRVE>) PxPUP PxCR Function Output Enable 1 0 PxFR1 1 Function Output PxDATA ...
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Type T12 PxPUP (Pull-up Control) PxCR (Output Control) Function Output Enable PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE> Function 1 Output 0 0 ...
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Block Diagrams of Ports 8.3.14 Type T13 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE>) 1 Function ...
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Type T14 PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE>) Function 1 Output N-chanel 0 Open-drain 0 1 Figure 8-14 Port Type T14 ...
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Block Diagrams of Ports 8.3.16 Type T15 PxPUP (Pull-up Control) PxCR (Output Control) PxFR2 (Function Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Drive Disable in STOP Mode Set by <DRVE> Function 1 Function 1 ...
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Type T16 PxPUP (Pull-up Control) PxCR (Output Control) PxFR2 (Function Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Function Input1 Function Input2 Drive Disable in STOP Mode Set by <DRVE> Function 1 ...
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Block Diagrams of Ports 8.3.18 Type T17 Analog Input Drive Disable in STOP Mode PxPUP (Pull-up Control) PxIE (Input Control) Port Read Figure 8-17 Port Type T17 Page 172 TMPM330FDFG/FYFG/FWFG <DRVE> RESET Input Port ...
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Type T18 PxPUP (Pull-up Control) PxFR1 (Function Control) PxIE (Input Control) Port Read Function Input Analog Input Drive Disable in STOP Mode Set by <DRVE>) Figure 8-18 Port TypeT18 Page 173 TMPM330FDFG/FYFG/FWFG RESET I/O Port ...
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Appendix (Port setting List) 8.4 Appendix (Port setting List) The following table shows the register setting for each function. Initialization of the ports where the [・] does not exist in the "After reset" field is set to "0" for ...
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Port B Setting Table 8-7 Port Setting List (Port B) Port Pin Type Input Port Output Port PB0 T11 TDO(Output)/ SWV(Output) Input Port PB1 T2 Output Port TDI(Input) Input Port PB2 T2 Output Port TRST(Input) Input Port PB3 T1 ...
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Appendix (Port setting List) 8.4.3 Port C Setting Table 8-8 Port Setting List (Port C) 8.4.4 Port D Setting Table 8-9 Port Setting List (Port D) Pin PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Port Pin Function Type ...
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Port E Setting Table 8-10 Port Setting List (Port E) Port Pin Function Type Input Port PE0 T10 Output Port TXD0(Output) Input Port PE1 T4 Output Port RXD0(Input) Input Port Output Port PE2 T16 SCLK0(Input) SCLK0(Output) CTS0(Input) Input Port ...
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Appendix (Port setting List) 8.4.6 Port F Setting Table 8-11 Port Setting List (Port F) Port Pin Type PF0 T10 PF1 T4 PF2 T16 PF3 T4 PF4 T13 PF5 T13 PF6 T13 PF7 T8 After re- Function PFCR set ...
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Port G Setting Table 8-12 Port Setting List (Port G) Port Pin Type Input Port Output Port PG0 T13 SO0(Output) SDA0(Input/Output) Input Port Output Port PG1 T13 SI0(Input) SCL0(Input/Output) Input Port Output Port PG2 T13 SCK0(Input) SCK0(Output) Input Port ...
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Appendix (Port setting List) 8.4.8 Port H Setting Table 8-13 Port Setting List (Port H) Pin PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 Note:The PH0 input and pull-up are enabled and act as BOOT input pin while a ...