TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 71

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8.1.2.3 Executing an ISR
user.
occur again upon return to normal program execution.
8.1.2.4
the currently executing ISR and services the newly detected exception.
(1)
(2)
SP_main or SP_process.
priority than all stacked exceptions, the CPU returns to the ISR of the pending exception.
the highest priority pending exception, the CPU returns to the last stacked ISR.
and entering another. This is called “tail-chaining”.
An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the
An ISR may need to include code for clearing the interrupt request so that the same interrupt will not
For details about interrupt handling, see “8.5 Interrupts”.
If a higher priority exception occurs during ISR execution for the current exception, the CPU abandons
When returning from an ISR, the CPU takes one of the following actions:
If a pending exception exists and there are no stacked exceptions or the pending exception has higher
In this case, the CPU skips the pop of eight registers and push of eight registers when exiting one ISR
If there are no pending exceptions or if the highest priority stacked exception is of higher priority than
If there are no pending or stacked exceptions, the CPU returns to the previous program.
When returning from an ISR, the CPU performs the following operations:
Pops the eight registers (PC, xPSR, r0 to r3, r12 and LR) from the stack and adjust the SP.
Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which
interrupt to return to.
If returning to an exception (Handler Mode), SP is SP_main. If returning to Thread Mode, SP can be
Execution after returning from an ISR
Exception exit sequence
Tail-chaining
Returning to the last stacked ISR
Returning to the previous program
Pop eight registers
Load current active interrupt number
Select SP
Exception exit
Under development
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TMPM330