TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 233
TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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INTRX0 Interrupt request)
INTRX0 Interrupt request)
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
Receive data
read timing
Receive data
read timing
RBFULL
RBFULL
OERR
If data cannot be read from buffer 2
RXD0
RXD0
(Note) To receive data, SC0MOD <RXE> must always be set to “1” (receive enable) in the
Fig. 11-13 Receive Operation in the I/O Interface Mode (SCLK0 Input Mode)
SCLK output / SCLK input mode.
SCLK input mode
The INTRX receive interrupt is generated each time received data is moved to received
buffer 2.
In the SCLK input mode, receiving double buffering is always enabled, the received frame
can be moved to receive buffer 2 and receive buffer 1 can receive the next frame
successively.
If data is read from buffer 2
bit 0
bit 0
Under development
bit 1
bit 1
Page221
bit 5
bit 5
bit 6
bit 6
bit 7
bit 7
bit 0
bit 0
TMPM330
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