TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 80

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8 Exceptions
8.5.2.2
(1)
Disabling interrupt by CPU
any unexpected interrupt on the way.
basically. Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then
enable the interrupt by the CPU.
unexpected interrupt. First, configure the precondition. Secondly, clear the data related to the
interrupt in the clock generator and then enable the interrupt.
them.
Interrupt Clear-Enable Register. Each bit of the register, of which default setting is disabled, is
assigned to a single interrupt source.
● NVIC register
Interrupt Clear-Enable<m>
(Note)
When preparing for an interrupt, you need to pay attention to the order of configuration to avoid
To configure the clock generator, you must follow the order indicated here not to cause any
The following sections are listed in the order of interrupt handling and describe how to configure
(1) Disabling interrupt by CPU
(2) CPU registers setting
(3) Preconfiguration 1 (Interrupt from external pin)
(4) Preconfiguration 2 (interrupt from peripheral function)
(5) Preconfiguration 3 (Interrupt Set-Pending Register)
(5) Configuring the clock generator
(6) Enabling interrupt by CPU
Initiating an interrupt or changing its configuration must be implemented in the following order
To make the CPU for not accepting any interrupt, write “1” to the corresponding bit of the
Preparation
m: corresponding bit
Under development
Page68
←
“1” (interrupt disabled)
TMPM330