TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 264

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12 Serial Bus Interface (SBI)
12.6.2
Generating the Start Condition and a Slave Address
Settings in main routine
Example of INTSBI0 interrupt routine
Clears the interrupt request.
Processing
End of interrupt
Reg.
Reg.
if Reg.
Then
SBIxCR1 ← X X X 1 0 X X X
SBIxDR1 ← X X X X X X X X
SBIxCR2 ← 1 1 1 1 1 0 0 0
Master mode
In the master mode, the following steps are required to generate the start condition
and a slave address.
First, ensure that the bus is free (<BB> = “0”). Then, write “1” to SBIxCR1 <ACK> to
select the acknowledgment mode. Write to SBIxDBR a slave address and a direction
bit to be transmitted.
When <BB> = “0,” writing “1111” to SBIxCR2 <MST, TRX, BB, PIN> generates the
start condition on the bus. Following the start condition, the SBI generates nine clocks
from the SCL pin. The SBI outputs the slave address and the direction bit specified at
SBIxDBR with the first eight clocks, and releases the SDA line in the ninth clock to
receive an acknowledgment signal from the slave device.
The INTSBIx interrupt request is generated on the falling of the ninth clock, and <PIN>
is cleared to ”0.” In the master mode, the SBI holds the SCL line at the “L” level while
<PIN> is “0.” <TRX> changes its value according to the transmitted direction bit at
generation of the INTSBIx interrupt request, provided that an acknowledgment signal
has been returned from the slave device.
≠ 0x00
← SBISR
← Reg. e 0x20
7 6 5 4 3 2 1 0
Under development
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Ensures that the bus is free.
Selects the acknowledgement mode.
Specifies the desired slave address and direction.
Generates the start condition.
TMPM330