TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 359

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

Variable S/H time
ADCLK
Example: If fsys = fc = 32 MHz/ 54MHz
15.3 Conversion Clock
fc
1
1/2
1/4
Conversion
clock
40MHz
(Note) Please do not change the analog to digital conversion clock setting during the
Prescaler [ADDCLK2:0]
● The conversion time is calculated by the 46 conversion clock.
Bi t symbol
Read/Write
After reset
Function
analog to digital conversion.
÷1
S/H time 40MHz
Conversion clk*8 （0.2 μs）
Conversion clk*16 （0.4 μs）
Conversion clk*24 （0.6 μs）
Conversion clk*32 （0.8 μs）
Conversion clk*64 （1.6 μs）
Conversion clk*128 （3.2 μs） 4.15μs
Conversion clk*512 （12.8 μs） 13.75μs
÷2
Select the A/D sample hold time
1100: 128 conversion clock
The setup other than those above: r eserved
Fig. 15-14 A/D Conversion Clock Setting Register
1000: 8 conversion clock
1010: 24 conver sion clock
0011: 64 conver sion clock
TSH3
R/W
7
1
÷4
A/D Conversion Clock Setting R egister
Fig. 15-15 A/D Conversion Time
tSH2
R/W
6
1.15μs
2.3μs
4.6μs
0
÷8
tconv.( conversion time )
Under development
1101: 512 conver sion clock
1011: 32 conversion clock
1001: 16 conversion clock
÷16
tSH1
Page347
R/W
5
0
40MHz
ADDCLK2:0
tconv.（ conversion time ）
1.15μs
1.35μs
1.55μs
1.75μs
2.55μs
tSH0
R/W
4
0
"0" is read.
3
R
0
1.44μs
2.88μs
5.75μs
Select the A/D prescaler output
000: fc
001: fc／2
010: fc／4
011: fc／8
100: fc／16
111:reserved
tconv.（ conversion time ）
ADCLK2
R/W
2
0
ADCLK
32MHz
ADCLK1
R/W
1
0
ADCL K0
TMPM330
R/W
0
0