TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 281

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8-bit receive mode
Set the control register to the receive mode. Then writing “1” to SBIxCR1 <SIOS> enables
reception. Data is taken into the shift register from the SI pin, with the least-significant bit
(LSB) first, in synchronization with the serial clock. Once the shift register is loaded with the
8-bit data, it transfers the received data to SBIxDBR and the INTSBIx (buffer-full) interrupt
request is generated to request reading the received data. The interrupt service program
then reads the received data from SBIxDBR.
state until the received data is read from SBIxDBR.
external clock. The maximum data transfer rate varies, depending on the maximum latency
between generating the interrupt request and reading the received data.
Reception can be terminated by clearing <SIOS> to “0” or setting <SIOINH> to “1” in the
INTSBIx interrupt service program. If <SIOS> is cleared, reception continues until all the
bits of received data are written to SBIxDBR. The program checks SBIxSR <SIOF> to
determine whether reception has come to an end. <SIOF> is cleared to “0” at the end of
reception. After confirming the completion of the reception, last received data is read. If
<SIOINH> is set to “1,” the reception is aborted immediately and <SIOF> is cleared to “0.”
(The received data becomes invalid, and there is no need to read it out.)
INTSBIx interrupt
In the internal clock mode, the serial clock will be stopped and automatically be in the wait
In the external clock mode, shift operations are executed in synchronization with the
(Note) The contents of SBIxDBR will not be retained after the transfer mode is
SBIxCR1 ← 0 1 1 1 0 X X X
SBIxCR1 ← 1 0 1 1 0 0 0 0
Reg.
changed. The ongoing reception must be completed by clearing <SIOS> to
“0” and the last received data must be read before the transfer mode is
changed.
← SBIxDBR
7 6 5 4 3 2 1 0
Under development
Page269
Selects the receive mode.
Starts reception.
Reads the received data.
TMPM330