TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 226

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TMPM330FWFG

Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM330FWFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM330FWFG
Manufacturer:
Toshiba
Quantity:
10 000
11 Serial Channel (SIO)
11.4.10 TX FIFO configuration register
SC0TFC
<TFCS>:
<TFIS>:
<TIL1:0>:
(Note)
bit Symbol
Read/Write
After reset
TIL1 is ignored when FDPX1:0 = 11 (full duplex).
Function
Clears TX FIFO.
Setting “1” clears TX FIFO and “0” is always read.
Selects interrupt generation condition.
0: An interrupt is generated when the data reaches to the specified fill level.
1: An interrupt is generated when the data reaches to the specified fill level or the data
cannot reach the
specified fill level at the time new data is read.
Selects FIFO fill level
00
01
10
11
Other than full
duplex
Empty
1byte
2byte
3byte
TX FIFO
clear
1:Clear
Always
reads “0”.
TFCS
W
7
0
1: when the
data reaches
to the
specified fill
level or the
data cannot
reach the
Select
interrupt
generation
condition
0: when the
data
reaches to
the
specified fill
level.
specified fill
level at the
time
data
read.
TFIS
R/W
(see note).
6
0
new
Under development
Full duplex
Empty
1byte
Empty
1byte
is
Page214
“0” is read.
5
4
R
0
3
2
FIFO fill level to
generate TX interrupts.
00:Empty
01:1byte
10:2byte
11:3byte
Note: TIL1 is ignored
when FDPX1:0=11 (full
duplex).
TIL1
1
0
R/W
TMPM330
TIL0
0
0

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