TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 206

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11 Serial Channel (SIO)
11.3.7
11.3.8
Receive buffer 2
Receive buffer 1
Receive interrupt
Receive FIFO Buffer
Receive FIFO Operation
The following example describes the case a 4-byte data stream is received in the half duplex
mode:
SC0RFC<7:6>=01: Clears receive FIFO and sets the condition of interrupt generation.
SC0RFC<1:0>=00: Sets the interrupt to be generated at fill level 4.
SC0FCNF <4:0>=10111: Automatically inhibits continued reception after reaching the fill level.
The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill
level.
In this condition, 4-byte data reception may be initiated by setting the half duplex transmission
mode and writing “1” to the RXE bit. After receiving 4 bytes, the RXE bit is automatically
cleared and the receive operation is stopped (SCLK is stopped).
RX FIFO
setting the wake-up function SC0MOD0 <WU> to “1.” In this case, the interrupt INTRX0 will
be generated only when SC0CR <RB8> is set to “1.”
In addition to the double buffer function already described, data may be stored using the
receive FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the
SC0MOD1 register, the 4-byte receive buffer can be enabled. Also, in the UART mode or
I/O interface mode, data may be stored up to a predefined fill level. When the receive FIFO
buffer is to be used, be sure to enable the double buffer function.
If data with parity bit is to be received in the UART mode, parity check must be performed
each time a data frame is received.
I/O interface mode with SCLK output:
RBFLL
RXE
Fig. 11-3 Receive FIFO Operation
1 byte
Under development
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1 byte
2 byte
1 byte
3 byte
2 byte
1 byte
2 byte
3 byte
4 byte
3 byte
2 byte
1 byte
4 byte
4 byte
3 byte
2 byte
1 byte
TMPM330