TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 224

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11 Serial Channel (SIO)
SC0FCNF
11.4.8
<RFST>:
<TFIE>:
<RFIE>:
<RXTXCNT>:
<CNFG>:
(Note)
FIFO configuration register
bit Symbol
Read/Write
After reset
Regarding TX FIFO, the maximum number of bytes being configured is always
available. The available number of bytes is the bytes already written to the TX FIFO.
Function
When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected
note)
0: The maximum number of bytes of the FIFO configured (see also <CNFG>).
1: Same as the fill level for receive interrupt generation specified by SC0RFC <RIL1:0>.
When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter.
When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter.
Enables FIFO.
If enabled, the SCOMOD1 <FDPX1:0> setting automatically configures FIFO as follows:
(The type of TX/RX can be specified in the mode control register 1
SC0MOD1<FDPX1:0>).
Half duplex
RX
Half duplex
TX
Full duplex
Controls automatic disabling of transmission and reception.
The mode control register SCOMOD1 <FDPX1:0> is used to set the types of TX/RX.
Setting “1” enables to operate as follows.
Half duplex
RX
Half duplex
TX
Full duplex
.
Be sure to write “000”.
Reserved
7
0
RX FIFO 4byte
TX FIFO 4byte
RX FIFO 2byte ＋ TX FIFO 2byte
When the RX FIFO is filled up to the specified number of valid bytes,
SC0MOD0<RXE> is automatically set to “0” to inhibit further
reception.
When the TX FIFO is empty, SC0MOD1<TXE> is automatically set
to “0” to inhibit further transmission.
When either of the above two conditions is satisfied, TXE/RXE are
automatically set to “0” to inhibit further transmission and
reception.
Reserved
6
0
Under development
Reserved
Page212
5
0
Bytes used
0:
Maximum
1:Same as
FILL level
of RX FIFO
in RX
FIFO
RFST
4
0
R/W
TX interrupt
for TX FIFO
0: Disabled
1: Enabled
TFIE
3
0
RX
interrupt for
RX FIFO
0:Disabled
1: Enabled
RFIE
2
0
RXTXCNT
Automatic
disable of
RXE/TXE
0:None
1:Auto
1
0
disab
le
TMPM330
FIFO
enable
0:
Disabled
1:
Enabled
CNFG
0
0
(see