TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 307

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13.3.1.4 Enabling Reception
13.3.1.5 Reception
reception by enabling the CECREN <CECREN> bit. Detecting a start bit initiates the reception.
set.
receive interrupt is generated and it causes the CECRSTAT <CECRIEND> bit to be set. Same as the
other data, the ACK bit that monitored the CEC line is stored instead of the one generated in the
CEC circuit.
indicating “1”. After detecting the final data block, CEC waits for a next start bit.
(Note)
After configuring the CECADD, CECRCR1, CECRCR2 and CECRCR3 registers, CEC is ready for
After detecting a start bit, a start bit interrupt is generated, and the CECRSTAT <CECRISTA> bit is
Upon receiving a byte of data, the EOM and ACK bits, they are stored in the CECRBUF register. A
The reception continues from the first data block until the final data block that has the EOM bit
Changing the configurations of the CECADD, CECRCR1, CECRCR2 and CECRCR3
registers during transmission or reception may harm its proper operation. Before
the change of the registers shown below, set the CECREN <CECREN> bit to
disable the reception and read the <CECREN> bit and the CECTEN <CECTEN> bit
to ensure that the operation is stopped.
CECADD
CECRCR1
CECRCR2
CECRCR3
<CECHNC><CECLNC>
<CECMIN><CECMAX>
<CECOTH>
<CECSWAV0><CECSWAV1>
<CECSWAV2><CECSWAV3>
<CECWAV0><CECWAV1>
<CECWAV2><CECWAV3>
<CECADD15:0>
Under development
Page295
Logical address
Noise cancellation time
Time to identify cycle error
Data reception at logical address
discrepancy
Start bit detection
Waveform error detection (when
enabled)
TMPM330