TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 221

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

SC0MOD2
11.4.6
<TBEMP>:
<RBFLL>:
<TXRUN>:
<SBLEN>:
<DRCHG>:
<WBUF>:
<SWRST1:0>:
(Note 1)
(Note 2)
(Note 3)
Mode control register 2
bit Symbol
Read/Write
After reset
While data transmission is in progress, any software reset operation must be
A software reset requires 2 clocks-duration at the time between the end of
A software reset initializes other bits. Resetting a mode register and a control
executed twice in succession.
recognition and the start of execution of software reset instruction.
register are needed.
Function
This flag shows that the transmit double buffers are empty. When data in the transmit
double buffers is moved to the transmit shift register and the double buffers are empty,
this bit is set to “1.” Writing data again to the double buffers sets this bit to “0.”
If double buffering is disabled, this flag is insignificant.
This is a flag to show that the receive double buffers are full. When a receive operation
is completed and received data is moved from the receive shift register to the receive
double buffers, this bit changes to “1” while reading this bit changes it to “0.”
If double buffering is disabled, this flag is insignificant.
This is a status flag to show that data transmission is in progress.
<TXRUN> and <TBEMP> bits indicate the following status.
This specifies the length of stop bit transmission in the UART mode. On the receive
side, the decision is made using only a single bit regardless of the <SBLEN> setting.
Specifies the direction of data transfer in the I/O interface mode. In the UART mode, it is
fixed to LSB first.
This parameter enables or disables the transmit/receive buffers to transmit (in both
SCLK output/input modes) and receive (in SCLK output mode) data in the I/O interface
mode and to transmit data in the UART. When receiving data in the I/O interface mode (I
SCLK input) and UART mode, double buffering is enabled in both cases that 0 or 1 is
set to <WBUF> bit.
<TXRUN>
Overwriting “01” in place of “10” generates a software reset. When this software reset
is executed, the following bits and their internal circuits are initialized (see note 1, 2
and 3) .
SC0MOD0
SC0MOD1
SC0MOD2
1
0
Register
SC0CR
Transmit
buffer
empty flag
0: full
1: Empty
TBEMP
7
1
<TBEMP>
Receive
Buffer full
flag
0: Empty
1: full
RBFLL
1
0
-
RXE
TXE
TBEMP,RBFLL,TXRUN,
OERR,PERR,FERR
Under development
6
R
0
In
transmissio
n flag
0: Stop
1: Start
Transmission in progress
Transmission completed
Wait state with data in TX buffer
Page209
TXRUN
Bit
5
0
STOP bit
(for UART)
0: 1-bit
1: 2-bit
SBLEN
4
0
Setting
transfer
direction
0: LSB first
1: MSB first
DRCHG
Status
3
0
W-buffer
0: Disabled
1: Enabled
WBUF
R/W
2
0
SOFT RESET
Overwrite
“10”to reset.
SWRST1
1
0
TMPM330
SWRST0
“01”
0
0
on