TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 287
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (4Mb)
13.2.2
13.2.3
<I2CEC>:
<CECEN>:
<CECADD15:0>:
(Note)
CEC Enable Register [CECEN]
Logical Address Register [CECADD]
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Read/Write
bit Symbol
After reset
Function
Function
Function
A broadcast message is received regardless of the register setting.
By allocating a logical address of a device to 15, logical “0” is sent as an ACK
response to the broadcast message.
Controls the CEC operation at the IDLE mode.
Set this bit to “1” when using CEC at the IDLE mode.
The <I2CEC> and <CECEN> bits can be set simultaneously.
Specifies the CEC operation.
Enable CEC before using.
When the CEC operation is disabled, no clocks are supplied to the CEC module except
for the enable register. Thus power consumption can be reduced.
When CEC is disabled after it was enabled, each register setting is maintained.
Specifies the logical address assigned to CEC.
Multiple addresses can be set simultaneously since each bit corresponds with
each address.
CECADD
CECADD
address
address
Logical
Logical
15
15
15
7
7
7
7
CECADD
CECADD
address
address
Logical
Logical
14
14
14
6
6
6
6
Under development
CECADD
CECADD
Page275
address
address
Logical
Logical
13
13
13
5
5
5
5
“0” is read.
―
R
0
CECADD
CECADD
address
address
Logical
Logical
12
12
12
4
4
4
4
R/W
R/W
0
0
CECADD
CECADD
address
address
Logical
Logical
11
11
11
3
3
3
3
CECADD
CECADD
address
address
Logical
Logical
10
10
10
2
2
2
2
CEC
operation
at IDLE
0:
Disabled
1:
Enabled
CECADD
CECADD
address
address
Logical
Logical
I2CEC
R/W
1
9
1
0
9
9
1
1
TMPM330
CEC
operation
0:
Disabled
1:
Enabled
CECADD
CECADD
address
address
CECEN
Logical
Logical
R/W
0
8
0
0
8
8
0
0
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