TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 309

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13.3.1.7 ACK Response
response to the data block when destination address corresponds with the address set in the logical
address register. The header block sends logical “0” as an ACK response regardless of the bit
setting when detecting the addresses corresponding.
(ACK bit: logical “0”). “No” indicates that CEC does not output “0” as a response to the ACK signal
from a transmission device (ACK bit: logical “1”).
transmission device. The timing to stop output is the same as that of outputting logical “0” for
transmission. The timing can be specified with the CECTCR <CECDTRS2:0> bit.
<CECACKDIS>
(Reference)
Setting the CECRCR1 <CECACKDIS> bit enables to specify if logical “0” is sent or not as an ACK
The following lists the ACK responses.
“Yes” indicates that CEC outputs “0” as a response to the ACK signal from a transmission device
The following describes the ACK response timing.
“0” is output within 0.35 ms from detecting the falling edge of the ACK bit output from the
CECRCR1
Register setting
Transmission
Reception
The configuration of <CECDTRS2:0> is applied for transmission of the data bits and
the EOM bit.
(responding logical
（not responding
logical “0”）
“0”)
“0”
“1”
Within 0.35ms
0.6±0.2ms
Start outputting “0”
Under development
Conformity
Page297
Header block address
Yes
Discrepancy
<CECDTRS>
1.5ms-7cycle~1.5ms
No
Conformity
Yes
No
Data block address
Discrepancy
TMPM330
No
No