TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 331

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

14.2.11 Remote Control Receive Status Register [RMCRSTAT]
<RMCRLIF>:
<RMCLOIF>:
<RMCDMAXIF>:
<RMCEDIF>:
<RMCRLDR>:
<RMCRNUM6:0>:
(Note 1)
(Note 2)
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
This register is updated every time an interrupt is generated.
Writing to this register is ignored.
RMC keeps receiving 73 bit or more data unless reception is completed by detecting
the maximum data bit cycle or the excess low width. If so, the received data in the
data buffer may not be correct.
Function
Indicates that leader detection is the interrupt factor.
Indicates that low width detection is the interrupt factor.
Indicates that maximum data bit cycle detection is the interrupt factor.
Indicates that a remote control input falling edge interrupt is the interrupt factor.
Detects a leader of a received remote control signal
Indicates the number of bits received as remote control signal data. The number
cannot be monitored during reception. On completion of reception, the number is
stored.
RMCRLDR RMCRNU
Leader
detection
is
interrupt
factor?
0: No
1: Yes
Leader
detection
0: No
1: Yes
RMCRLIF
15
R
7
R
0
0
Low width
0: No
1: Yes
The number of received data bit
0000000:no data bit (only with leader)
0000001~1001000:1~72bit
1001001~1111111:73bit and more
RMCLOIF RMCDMAX
detection
is interrupt
factor?
Under development
14
M6
R
6
0
Maximum
data bit
cycle
detection
is interrupt
factor?
0: No
1: Yes
RMCRNU
Page319
13
M5
IF
R
5
0
1: Yes
RMCEDIF
Remote
control
input
falling
edge
interrupt
is
interrupt
factor?
0: No
RMCRNU
12
M4
R
4
0
”0” is read.
RMCRNU
11
M3
―
3
R
0
RMCRNU
10
M2
―
2
R
0
RMCRNU
M1
―
9
1
TMPM330
RMCRNU
M0
―
8
0