TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 291

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

<CECACKDIS>:
<CECHNC1:0>:
<CECLNC2:0>:
<CECMIN2:0>:
<CECMAX2:0>:
<CECDAT2:0>:
<CECTOUT1:0>:
<CECRIHLD>:
<CECOTH>:
(Note 1)
(Note 2)
(Note 3)
Changing the configurations during transmission or reception may harm its proper
A broadcast message is received regardless of the <CECOTH> register setting.
The settings in <CECHNC>, <CECLNC> and <CECDAT> are also used in receiving
an ACK response at transmission.
operation. Before the change, set the CECREN <CECREN> bit to disable the
reception and read the <CECREN> bit and the CECTEN <CECTEN> bit to ensure that
the operation is stopped.
Specifies if a receive error interrupt (maximum cycle error, buffer overrun and
Specifies if logical “0” is sent or not as an ACK response to the data block when
destination address corresponds with the address set in the logical address
register. (The header block sends logical “0” as an ACK response regardless of the
bit setting when detecting the addresses corresponding).
Specifies the time of the noise cancellation for each sampling clock cycle when
detecting “1”.
It is considered as noise if “1”s of the same number as the specified cycles are not
sampled.
Specifies the time of the noise cancellation for each sampling clock cycle when
detecting “0”.
It is considered as noise if “0”s of the same number as the specified cycles are not
sampled.
Specifies the minimum time to identify a valid bit.
Enables to specify it for each sampling clock cycle between the ranges of -4 to +3
cycles from approx. 2.05 ms.
An interrupt is generated and “0” is output to CEC for approx. 3.6 ms when one bit
cycle is shorter than the specified time.
Specifies the maximum time to identify a valid bit.
Enables to specify it for each sampling clock cycle between the ranges of -4 to +3
cycles from approx. 2.75 ms.
An interrupt is generated when one bit cycle is longer than the specified time.
Specifies the point of determining the data as 0 or 1.
Enables to specify it per two sampling clock cycles between the ranges of + or - 6
cycles from approx. 1.05 ms.
waveform error) is suspended or not.
Setting “1” generates no interrupt at the error detection. If data continues to an ACK
bit, an ACK response is executed by a reversed logic. If the subsequent bits are
interrupted, it is determined as a timeout, based on the setting in <CECTOUT>.
After the ACK response or the timeout determination, an interrupt is generated.
Specifies if data is received or not when destination address does not correspond
with the address set in the logical address register.
Specifies the time to determine a timeout. Enables to specify it between 1 bit and 3
bits for each bit cycle.
This setting is used to detect a timeout occurs when the <CECRIHLD> bit is valid.
Under development
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TMPM330