TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 67

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

(1)
from external interrupt pins or peripheral functions.
condition occurs during instruction execution.
violation to the Fault region.
used for releasing a standby mode, relevant settings must be made in the clock generator. For details,
refer to “8.5 Interrupts”.
(2)
8.1.2.1
that exception. Memory Management, Bus Fault and Usage Fault exceptions can be enabled or
disabled. If a disabled exception occurs, it is handled as Hard Fault.
Table 8-1 shows the priority of exceptions. “Configurable” means that you can assign a priority level to
Exception sources include instruction execution by the CPU, memory accesses, and interrupt requests
An exception occurs when the CPU executes an instruction that causes an exception or when an error
An exception also occurs by an instruction fetch from the Execute Never (XN) region or an access
An interrupt is generated from an external interrupt pin or peripheral function. For interrupts that are
If multiple exceptions occur simultaneously, the CPU takes the exception with the highest priority.
7-10
No.
16-
11
12
13
14
15
1
2
3
4
5
6
Exception occurrence
Exception detection
Exception Request and Detection
Interrupt
Management
Reset
Non-Maskable
Hard Fault
Memory
Bus Fault
Usage Fault
Reserved
SVCall
Debug Monitor
Reserved
PendSV
SysTick
External Interrupt
Exception type
Table 8-1 Exception Types and Priority
-3 (highest)
-2
-1
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Under development
Priority
Page55
Reset pin, WDT or SYSRETREQ
NMI pin or WDT
Fault that cannot activate because a higher-priority
fault is being handled or it is disabled
Exception from the Memory Protection Unit (MPU)
(Note 1)
Instruction fetch from the Execute Never (XN) region
Access violation to the Hard Fault region of the
memory map
Undefined instruction execution or other faults related
to instruction execution
System service call with SVC instruction
Debug monitor when the core is not halting
Pendable system service request
Notification from system timer
External interrupt pin or peripheral function (Note 2)
Description
TMPM330