TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 316

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13 Consumer Electronics Control (CEC)
13.3.2.3 Starting Transmission
13.3.2.4 Transmission
13.3.2.5 ACK Transmission and ACK Error Criterion
CECTCR and CECTBUF registers.
occurs. Thus you don’t need to set this bit for each a byte of data transmission.
line for specified bit cycles, start bit is transmitted. The CEC always checks if bus is free.
Transmission starts anytime if bus is free for specified bit cycles.
the shift register, and data transmission is started. When CEC starts transmitting the first bit of a byte
of data, a transmit interrupt is generated. It sets the CECTSTAT <CECTISTA> bit. Subsequent to the
transmit interrupt, a byte of next data can be set to the transmit buffer.
This is the end of a byte of data transmission.
check as described above. Generation of this interrupt, which means the end of a sequence of
transmission operation, sets the CECTSTAT <CECTIEND> bit, and clears the CECTEN <CECTEN>
bit.
determined as an error. If this bit is not set, the ACK response of logical “1” is determined as an error.
(Note)
Transmission is ready by setting the CECTEN <CECTEN> bit to start transmission after setting the
The <CECTEN> bit is never cleared to “0” until a transmit completion interrupt or an error interrupt
Next to the setting for starting transmission, CEC checks if a bus is free. If “1” is sampled as a CEC
After transmitting a start bit, a byte of data and the EOM data that are set in the buffer are sent to
Then 8 bit data, the EOM bit and the ACK bit are transmitted, and the ACK response is checked.
Data transfer continues in the above sequence until “1” is set to the EOM bit.
If “1” is set to the EOM, a transmit completion interrupt is generated subsequent to the ACK bit
A criterion of the ACK error differs depending on the CECTCR <CECBRD> bit.
If this bit is set, broadcast message is transmitted, and the ACK response of logical “0” is
Changing the configurations of the CECTCR register during transmission or
reception may harm its proper operation. Be careful if you change it during
transmission.
Under development
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TMPM330