TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 187

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.8 Applications using the Capture Function
Count clock
(Internal clock)
TB5IN0 pin input
(External trigger pulse)
Match with TB5RG0
Match with TB5RG1
Timer output TB5OUTpin
The capture function can be used to develop many applications, including those described below:
One-shot pulse output triggered by an external pulse is carried out as follows:
The 16-bit up-counter is made to count up by putting it in a free-running state using the prescaler
output clock. An external pulse is input through the TB5IN0 pin. A trigger is generated at the rising of
the external pulse by using the capture function and the value of the up-counter is taken into the
capture registers (TB5CP0).
The CPU must be programmed so that an interrupt INTCAP50 is generated at the rising of an
external trigger pulse. This interrupt is used to set the timer registers (TB5RG0) to the sum of the
TB5CP0 value (c) and the delay time (d), (c + d), and set the timer registers (TB5RG1) to the sum of
the TB5RG0 values and the pulse width (p) of one-shot pulse, (c + d + p).
TB5RG1 change must be completed before the next match.
In addition, the timer flip-flop control registers (TB5FFCR<TB5E1T1, TB5E0T1>) must be set to “11.”
This enables triggering the timer flip-flop (TB5FF0) to reverse when UC5 matches TB5RG0 and
TB5RG1. This trigger is disabled by the INTTB5 interrupt after a one-shot pulse is output.
Symbols (c), (d) and (p) used in the text correspond to symbols c, d and p in “Fig. 10-5 One-shot
Pulse Output (With Delay).”
One-shot pulse output triggered by an external pulse
Time difference measurement
One-shot pulse output triggered by an external pulse
Frequency measurement
Pulse width measurement
Fig. 10-5 One-shot Pulse Output (With Delay)
c
Put the counter in a free-running state.
Disable reverse when
data is taken into CAP5.
Taking data into the capture register (CAP5)
INTCAP50 generation
Under development
Delay time
Enable reverse
(d)
Page175
c + d
Enable
reverse
INTTB5 generation
Pulse width
(p)
c + d + p
INTTB5 generation
TMPM330