TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 108

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8 Exceptions
IMCGA
8.6.3
8.6.3.1
NVIC Registers
(Note 1)
(Note 2)
CG Interrupt Mode Control Register A
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
“0” is read. Active state setting of INT0 standby
“0” is read. Active state setting of INT1 standby
“0” is read. Active state setting of INT2 standby
“0” is read. Active state setting of INT3 standby
Refer to EMSTxx bit to know the active condition which is used for clearing
standby.
Please specify the bit for the edge first and then specify the bit for the
<INTxEN>. Setting them simultaneously is prohibited.
15
23
31
7
R
R
R
R
0
0
0
0
clear request. (101~111: setting
prohibited)
clear request. (101~111: setting
prohibited)
clear request. (101~111: setting
prohibited)
clear request. (101~111: setting
prohibited)
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCG02
EMCG12
EMCG22
EMCG32
14
22
30
6
0
0
0
0
Under development
EMCG21
EMCG01
EMCG11
EMCG31
R/W
R/W
R/W
R/W
13
21
29
Page96
5
1
1
1
1
EMCG00
EMCG10
EMCG20
EMCG30
12
20
28
4
0
0
0
0
standby clear request
standby clear request
standby clear request
standby clear request
Active state of INT0
Active state of INT1
Active state of INT2
Active state of INT3
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
EMST01
EMST11
EMST21
EMST31
11
19
27
3
0
0
0
0
R
R
R
R
EMST00
EMST10
EMST20
EMST30
10
18
26
2
0
0
0
0
“0” is read. INT0 clear
“0” is read. INT1 clear
“0” is read. INT2 clear
“0” is read. INT3 clear
17
25
1
R
9
R
R
R
0
0
0
0
input
0: Disable
1: Enable
input
0: Disable
input
0: Disable
1: Enable
input
0: Disable
1: Enable
1: Enable
INT0EN
INT1EN
INT2EN
INT3EN
TMPM330
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0