TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 167

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

TBnMOD
(0x4001_0xxC)
＜TBnCLK1:0＞:Selects the TMRBn timer count clock.
＜TBnCLE＞:Clears and controls the TMRBn up-counter.
＜TBnCPM1:0＞:Specifies TMRBn capture timing.
＜TBnCP0＞:Captures count values by software and takes them into capture register 0 (TBnCP0).
(Note 1)
(Note 2)
10.4.1.4 TMRB mode register (channels 0 thorough 9)
Read/Write
Read/Write
Read/Write
Read/Write
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
Function
“0”: Disables clearing of the up-counter.
“1”: Clears up-counter if there is a match with timer register 1 (TBnRG1).
“00”: Capture disable
“01”: Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN0 pin input.
“10”: Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN0 pin input.
“11”:Takes count values into capture register 0 (TBnCP0) upon rising of 16-bit timer match
The value read from bit 5 of TBnMOD is “1”.
Input from TBnIN0 and TBnIN1 is available only for channels TMRB0 thorough 6.
“0” is read. Write “0”.
output (TBxOUT) and into capture register 1 (TBnCP1) upon falling of TBxOUT
(TMRB0 and TMRB1:TB7OUT, TMRB2 through TMRB4:TB8OUT, TMRB5 and
TMRB6:TB9OUT).
Takes count values into capture register 1 (TBnCP1) upon rising of TBnIN1 pin input.
Takes count values into capture register 1 (TBnCP1) upon falling of TBnIN0 pin input.
31
23
15
R
R
R
7
R
0
0
0
0
R/W
30
22
14
R
R
R
6
0
0
0
0
TMRBn mode register(n=0~9)
Capture
control by
software
0: Capture
by software
1: Don't
care
Under development
TBnCP0
29
21
13
W
R
R
R
5
0
0
0
1
Page155
00: Disable Capture timing
00: Disable
01: TBnIN0 ↑ TBnIN1 ↑
10: TBnIN0 ↑ TBnIN1 ↓
11: TBnOUT ↑ TBnOUT ↓
Capture timing
TBnCPM1 TBnCPM0
28
20
12
R
R
R
4
0
0
0
0
27
19
11
R
R
R
3
0
0
0
0
Up-counter
control
0:
Clear/disable
1:
clear/enable
TBnCLE
R/W
26
18
10
R
R
R
2
0
0
0
0
Selects source clock
00: TBnIN0 pin input
01: φT1
10: φT4
11: φT16
TBnCLK1
25
17
R
R
9
R
1
0
0
0
0
TBnCLK0
24
16
R
R
8
R
0
0
0
0
0
TMPM330