TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 248

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

SBIxCR1
12 Serial Bus Interface (SBI)
<Bit 2：0><SCK2:0>: Select internal SCL output clock frequency
<Bit 0>< SWRMON：0>: Software reset status monitor
<Bit 7：5><BC2：0> : Select the number of bits per transfer
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Select the number of bits per
transfer (Note 1)
BC2
15
23
31
7
0
BC1
Fig. 12-4 I
R/W
14
22
30
6
0
Serial bus control register 1
Under development
BC0
13
21
29
2
5
0
C Bus Mode register
Page236
Acknowled
gment
clock
0: Not
1: Generate
This can be read as “0.”
This can be read as “0.”
This can be read as “0.”
generate
ACK
R/W
12
20
28
4
0
On writing <SCK2:0>: Select internal SCL output clock
frequency
On reading <SWRMON>: Software reset status monitor
Select the number of bits per transfer
000
001
010
011
100
101
110
111
<BC2:0>
R
R
R
0
1
0
0
0
000
001
010
011
100
101
110
111
This
be read as
“1.”
n=10
n=11
n=5
n=6
n=7
n=8
n=9
19
27
11
3
R
1
Software reset operation is in progress.
Software reset operation is not in progress.
can
clock cycles
Number of
196 kHz
149 kHz
101 kHz
61
34
18
reserved
When <ACK> = 0
9
Select internal SCL output clock
frequency (Note 2) and reset monitor.
8
1
2
3
4
5
6
7
SCK2
kHz
kHz
kHz
kHz
10
18
26
2
0
R/W
length
System clock: fsys
Clock gear
Frequency =
Data
8
1
2
3
4
5
6
7
SCK1
17
25
1
9
0
clock cycles
Number of
When <ACK> = 1
2
SWRMON
n
9
2
3
4
5
6
7
8
fsys
SCK0/
+ 72
TMPM330
R/W
16
24
0
8
1
: fc/1
(=40 MHz)
[ Hz ]
length
Data
8
1
2
3
4
5
6
7