TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 211
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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11.3.12 Transmit FIFO Buffer
11.3.13 Transmit FIFO Operation
Transmit buffer 1
Transmit buffer 2
TX FIFO
In addition to the double buffer function already described, data may be stored using the
transmit FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the
SC0MOD1 register, the 4-byte transmit buffer can be enabled. In the UART mode or I/O
interface mode, up to 4 bytes of data may be stored.
If data is to be transmitted with a parity bit in the UART mode, parity check must be performed
on the receive side each time a data frame is received.
TBEMP
INTTX0
TXE
I/O interface mode with SCLK output (normal mode):
The following example describes the case a 4-byte data stream is transmitted:
SC0TFC <7:6> = 01: Clears transmit FIFO and sets the condition of interrupt generation
SC0TFC <1:0> = 00: Sets the interrupt to be generated at fill level 0.
SC0FCNF <4:0> = 01011: Inhibits continued transmission after reaching the fill level.
In this condition, data transmission can be initiated by setting the transfer mode to half
duplex, writing 4 bytes of data to the transmit FIFO, and setting the <TXE> bit to “1.”
When the last transmit data is moved to the transmit buffer, the transmit FIFO interrupt is
generated. When transmission of the last data is completed, the clock is stopped and the
transmission sequence is terminated.
Fig. 11-8 Transmit FIFO Operation
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Under development
Page199
Data 3
Data 5
Data 4
Data 2
Data 6
Data 4
Data 6
Data 5
Data 3
Data 5
Data 6
Data 4
Data 6
Data 5
TMPM330
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