TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 104

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8 Exceptions
<bit28:7>
<bit29>
8.6.2.14 Vector Table Offset Register
<TBLOFF>
<TBLBASE> The vector table is in:
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Offset value
TBLOFF
0 = Code space
1 = SRAM space
Set the offset value from the top of the space specified in TBLBASE.
The offset must be aligned based on the number of exceptions in the table. This
means that the minimum alignment is 32 words that you can use for up to 16
interrupts. For more interrupts, you must adjust the alignment by rounding up to the
next power of two.
R/W
15
23
31
7
0
“0” is read.
R
0
14
22
30
6
Under development
Table base
TBLBA
R/W
SE
29
13
21
Page92
5
0
28
12
20
4
Offset value
Offset value
TBLOFF
TBLOFF
R/W
R/W
0
0
“0” is read.
19
27
11
3
R
0
Offset value
TBLOFF
R/W
10
18
26
2
0
17
25
9
1
TMPM330
16
24
0
8