TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 387
TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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17.5.3 Entering the Low Power Consumption Mode
adjusting seconds or resetting the clock, be sure to observe one of the following procedures:
3. Disabling the clock
1. After changing the clock setting registers, setting the PAGER<ADJUST> bit or setting the
2. After changing the clock setting registers, setting the PAGER<ADJUST> bit or setting the
To enter SLEEP mode, in which the system clock stops, after changing clock data,
RESTR<RSTTMR> bit, wait for one second for an interrupt to be generated.
RESTR<RSTTMR> bit, read the corresponding clock register values, <ADJUST> or
<RSTTMR> to make sure that the setting you have made is reflected.
again and enable the clock within one second before next 1Hz-interrupt.
Writing “0” to PAGER<ENATMR> disables clock operation including a carry.
Stop the clock after the 1Hz-interrupt. The sec. counter keeps counting. Set the clock
Fig. 17-4 Flowchart of the disabling clock
Under development
Writing the clock data
Enabling the clock
Disabling clock
Page375
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End
TMPM330
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