TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 266
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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12 Serial Bus Interface (SBI)
SCL pin
Write to SBIxDBR
SDA pin
<PIN>
INTS0 interrupt
request
12.6.3
INTSBIx interrupt
Transferring a Data Word
At the end of a data word transfer, the INTSBIx interrupt is generated to test <MST> to
determine whether the SBI is in the master or slave mode.
if MST = 0
Then
if TRX = 0
Then
if LRB = 0
Then
End of interrupt processing
(Note)
SBIxCR1 ← X X X X 0 X X X
SBIxDBR ← X X X X X X X X
Fig. 12-15 <BC2:0> = “000” and <ACK> = “1” (Transmitter Mode)
Master mode (<MST> = “1”)
Test <TRX> to determine whether the SBI is configured as a transmitter or a receiver.
Transmitter mode (<TRX> = “1”)
Test <LRB>. If <LRB> is “1,” that means the receiver requires no further data. The
master then generates the stop condition as described later to stop transmission.
If <LRB> is “0,” that means the receiver requires further data. If the next data to be
transmitted has eight bits, the data is written into SBIxDBR. If the data has different
length, <BC2:0> and <ACK> are programmed and the transmit data is written into
SBIxDBR. Writing the data makes <PIN> to”1,” causing the SCL pin to generate a
serial clock for transferring a next data word, and the SDA pin to transfer the data word.
After the transfer is completed, the INTSBIx interrupt request is generated, <PIN> is set
to “0,” and the SCL pin is pulled to the “L” level. To transmit more data words, test <LRB> again
and repeat the above procedure.
go to the slave-mode processing
go to the receiver-mode processing
go to processing for generating the stop condition
D7
X: Don’t care
1
D6
2
D5
3
Under development
Page254
D4
4
Specifies the number of bits to be transmitted and specify
whether ACK is required.
Writes the transmit data.
D3
5
D2
6
D1
7
D0
8
ACK
Master output
Slave output
9
Acknowledgment signal
from receiver
TMPM330
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