TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 355
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
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ADREG4CL
ADREG4CH
ADREG5DL
ADREG5DH
•
•
•
con verted value is stored. A read of a lower register (ADREGxL ) wi ll set this bit to "0”.
before both con version result storage registers (ADREGxH and ADREGxL) are read. A read of a flag will clear this bit to
"0”.
registers.
Bit 0 of the ADREG4CL/ADREG5DL is the A/D conversion result storage flag <ADRxRF>. It is set to "1" after an A/D
Bit 1 of the ADREG4CL/ADREG5DL is the over Run flag <OVRx>. It is se t to "1" if a conversion resul t i s o verwri tten
When re ading conversion result storage registers on a byte-by-byte basis, first read upper registers and then read lower
Converted channel x value
Bi t symbol
Read/Write
After reset
Bi t symbol
Read/Write
After reset
Bi t symbol
Read/Write
After reset
Bi t symbol
Read/Write
After reset
Function
Function
Function
Function
A/D conversion result
A/D conversion result
Store lo wer 2 bits of
Store lo wer 2 bits of
ADR41
ADR49
ADR51
ADR59
7
7
7
7
Fig. 15-10 A/D Conversion Result Register
Lower A/D Conversion Result Register 4C
Upper A/D Conversion Result Register 4C
Lower A/D Conversion Result Register 5D
Upper A/D Conversion Result Register 5D
A DREGxH
R
R
0
0
9
ADR40
ADR48
ADR50
ADR58
7
6
6
6
6
8
6
Under development
7
5
"0" is read.
"0" is read.
ADR47
ADR57
Page343
4
Store upper 8 bits of A/D conversion result
Store upper 8 bits of A/D conversion result
6
5
5
5
5
3
5
2
4
ADR46
ADR56
1
4
4
4
4
3
0
R
R
R
R
0
0
0
0
2
ADR45
ADR55
1
7
3
3
3
3
6
0
5
ADR44
ADR54
2
2
2
2
4
3
Over RUN
flag
0: Not
generate
1: Generate
Over RUN
flag
0: Not
generate
1: Generate
ADR43
ADR53
2
OVR4
OVR5
R
R
1
0
1
1
0
1
ADREGxL
1
0
TMPM330
Presence of
A/D
conversion
result storage
flag
1: Presence of
conversion
result
A/D
conversion
result storage
flag
conversion
result
ADR4RF
ADR5RF
ADR42
ADR52
0
R
0
0
0
R
0
0
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