TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 204
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Company
Part Number
Manufacturer
Quantity
Price
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11 Serial Channel (SIO)
11.3.3
11.3.4
11.3.5
11.3.6
•
•
•
•
Serial Clock Generation Circuit
Receive Counter
Receive Control Unit
Receive Buffer
I/O interface mode
Asynchronous (UART) mode :
I/O interface mode:
Asynchronous (UART) mode:
The receive counter is a 4-bit binary counter used in the asynchronous (UART) mode and is
up-counted by SIOCLK. Sixteen SIOCLK clock pulses are used in receiving a single data bit
while the data symbol is sampled at the seventh, eighth, and ninth pulses. From these three
samples, majority logic is applied to decide the received data.
The receive buffer is of a dual structure to prevent overrun errors. The first receive buffer (a
shift register) stores the received data bit-by-bit. When a complete set of bits have been
stored, they are moved to the second receive buffer (SC0BUF). At the same time, the
receive buffer full flag (SC0MOD2 “RBFLL”) is set to “1” to indicate that valid data is stored
in the second receive buffer. However, if the receive FIFO is set enabled, the receive data is
moved to the receive FIFO and this flag is immediately cleared.
If the receive FIFO has been disabled (SCOFCNF <CNFG> = 0 and SC0MOD1<FDPX1:0>
=01), the INTRX0 interrupt is generated at the same time. If the receive FIFO has been
enabled (SCNFCNF <CNFG> = 1 and SC0MOD1<FDPX1:0> = 01), an interrupt will be
generated according to the SC0RFC <RIL1:0> setting.
This circuit generates basic transmit and receive clocks.
In the SCLK output mode with SC0CR <IOC> set to “0,” the RXD0 pin is sampled on the
rising edge of the shift clock output to the SCLK0 pin.
In the SCLK input mode with SC0CR <IOC> set to “1,” rising and falling edges are
detected according to the SC0CR <SCLKS> setting to generate the basic clock.
According to the settings of the serial control mode register SC0MOD0 <SC1:0>, either
the clock from the baud rate register, the system clock (f
the TMRB9 timer, or the external clock (SCLKO pin) is selected to generate the basic
clock, SIOCLK.
In the SCLK input mode with SC0CR <IOC> set to “1,” the serial receive data RXD0 pin
is sampled on the rising or falling edge of SCLK input depending on the SC0CR
<SCLKS> setting.
The receive control unit has a start bit detection circuit, which is used to initiate receive
operation when a normal start bit is detected.
In the SCLK output mode with the SC0CR <IOC> serial control register set to “0,” the
output of the previously mentioned baud rate generator is divided by 2 to generate the
basic clock.
Under development
Page192
SYS
), the internal output signal of
TMPM330
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