TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 357
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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ADREGSPL
ADREGSPH
•
•
•
va lue is stored. A read of a lower register (ADREGxL) will set this bit to "0."
co nversion result storage register s (ADREGxH and ADREGxL) are read. A read of a flag will clear this bit to "0”.
lowe r registers.
Bit 0 of the ADREGSP is the A/D conversion result storage flag <ADRxRF>. It is set to "1" after an A/D converted
Bit 1 of the ADREGSP is the over RUN flag <OVRx>. It is set to "1" if a conversion result is overwritten before both
When reading conversion result storage registers on a byte-by-byte basis, first read upper registers and then read
Converted channel x value
Bi t symbol
Read/Write
After reset
Bi t symbol
Read/Write
After reset
Function
Function
ADRSP1
A/D conversion result
ADRSP9
Store lo wer 2 bits of
7
7
Fig. 15-12 A/D Conversion Result Register
U pper A/D Conversion Result Register SP
Lower A/D Conversion Result Register SP
A DREGxH
R
0
9
ADRSP0
ADRSP8
7
6
6
8
6
Under development
7
5
"0" is read.
ADRSP7
Page345
4
Store upper 8 bits of A/D conversion result
6
5
5
3
5
2
ADRSP6
4
1
4
4
3
0
R
R
0
0
2
ADRSP5
1
7
3
3
6
0
ADRSP4
5
2
2
4
3
Over RUN
flag
0: Not
generate
1: Generate
ADRSP3
OVRSP
2
R
1
0
1
ADREGxL
1
0
TMPM330
ADRS PRF
A/D
conversion
result storage
flag
1:
Presence of
conversion
result
ADRSP2
0
R
0
0
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