TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 436

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

18 Flash Memory Operation
(3) Reset
(Note 1) Command sequences are executed from outside the flash memory area.
(Note 2) Each bus write cycle must be sequentially executed by 32-bit data transmit
(Note 3) For the command sequencer to recognize a command, the device must be in the
(Note 4) Upon issuing a command, if any address or data is incorrectly written, be sure to
command write operation is in accordance with a predefined specific sequence. If any bus
write cycle does not follow a predefined command write sequence, the flash memory will
terminate the command execution and return to the read mode.
command. While a command sequence is being executed, access to the flash
memory is prohibited. Also, don't generate any interrupt (except debug exceptions
when a DSU probe is connected).If such an operation is made, it can result in an
unexpected read access to the flash memory and the command sequencer may not
be able to correctly recognize the command. While it could cause an abnormal
termination of the command sequence, it is also possible that the written command
is incorrectly recognized.
read mode prior to executing the command. Be sure to check before the first bus
write cycle that the FLCS RDY/BSY bit is set to "1." It is recommended to
subsequently execute a Read command.
perform a software reset to return to the read mode again.
A hardware reset is used to cancel the operational mode set by the command write
operation when forcibly termination during auto programming/ erasing or abnormal
termination during auto operations occurs. The flash memory has a reset input as the
memory block and it is connected to the CPU reset signal. Therefore, when the RESET
input pin of this device is set to V
watch dog timer, the flash memory will return to the read mode terminating any automatic
operation that may be in progress. It should also be noted that applying a hardware reset
during an automatic operation can result in incorrect rewriting of data. In such a case, be
sure to perform the rewriting again.
Refer to Section 18.2.1 "Reset Operation" for CPU reset operations. After a given reset
input, the CPU will read the reset vector data from the flash memory and starts operation
after the reset is removed.
Hardware reset
Under development
Page424
IL
or when the CPU is reset due to any overflow of the
TMPM330