TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 394

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

18 Flash Memory Operation
18.2.1
Either the Single Chip or Single Boot operation mode can be selected by externally setting the level
of the BOOT (PH0) pin while the device is in reset status.
After the level is set, the CPU starts operation in the selected operation mode when the reset
condition is removed. Regarding the BOOT (PH0) pin, be sure not to change the levels during
operation once the mode is selected.
The mode setting method and the mode transition diagram are shown below:
(Note 1) Regarding power-on reset of devices with internal flash memory;
(Note 2) While flash auto programming or deletion is in progress, at least 0.5 microseconds
Single chip mode
Single boot mode
Reset Operation
To reset the device, ensure that the power supply voltage is within the operating voltage range,
that the internal oscillator has been stabilized, and that the
minimum duration of 12 system clocks (0.3 μs with 40MHz operation; the "1/1" clock gear mode
is applied after reset).
Single chip mode
Normal mode
for devices with internal flash memory, it is necessary to apply "0" to the RESET
inputs upon power on for a minimum duration of 300 microseconds regardless of
the operating frequency.
of reset period is required regardless of the system clock frequency.
condition, it takes approx. 2 ms to enable reading after reset.
User to set the
switch method
Operation mode
Fig. 18-2 Mode Transition Diagram
Table 18-2 Operation Mode Setting
boot mode
User
Under development
Page382
Onboard
programming mode
boot mode
Single
RESET
0 → 1
0 → 1
Pin
RESET
Reset state
BOOT (PH0)
input is held at "0" for a
1
0
TMPM330
In this