TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 116

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

9 Input/Output Ports
9.2
9.2.1
PA0, PB0
[When used for debug (PxFR<n>=1) and
PF7, PG3, PJ0-3, PJ6, PJ7
[When used for interrupt (PxFR<n>=1) and
Other ports
9.2.2
output is enabled (PxCR<n>=1)]
input is enabled (PxIE<n>=1)
Control Register.
m
and PxCR are enabled.
fully effective. Configure PA1 to function as a general-purpose port if the debug function is not used.
If <DRVE>=0, both input and output are disabled in STOP mode except for some ports even if PxIE
Input and output in STOP mode are enabled/disabled by the STBYCR2<DRVE> bit in the Standby
The differences are summarized in the table shown below.
If PA1 is configured as a debug function pin, it prevents the low power consumption mode from being
If PxIE or PxCR is enabled with <DRVE>=1, input or output is enabled respectively in STOP
Port Functions
Port States in STOP Mode
Precaution for Mode Transition
Port
]
×
○
:
:
Input or output enabled
Input or output disabled
Output
Output
Output
Input
Input
Input
I/O
Under development
Page104
Disabled when data is invalid.
Enabled when data is valid.
<DRVE>=0
○
×
×
×
×
Disabled when data is invalid.
Enabled when data is valid.
Depends on PxCR<n>.
Depends on PxCR<n>.
Depends on PxIE<n>.
Depends on PxIE<n>.
<DRVE>=1
○
TMPM330