TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 323
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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14.2.2
14.2.3
<I2RMC>:
<RMCEN>:
<RMCREN>:
(Note)
Remote Control Enable Register [RMCEN]
Remote Control Receive Enable Register [RMCREN]
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
Enable the <RMCREN> bit after setting the RMCxRCR1, RMCxRCR2 and RMCxRCR3.
Controls RMC operation in IDLE mode.
Set “1” to enable RMC in IDLE Mode.
This bit and the <RMCEN> bit can be set simultaneously.
Controls RMC operation.
To allow RMC to function, enable the RMCEN bit first. If the operation is disabled, all the
clocks for RMC except for the enable register are stopped, and it can reduce power
consumption.
If RMC is enabled and then disabled, the settings in each register remain intact.
Controls reception of RMC.
Setting this bit to “1” enables reception.
7
7
Under development
6
6
Page311
5
5
”0” is read.
―
R
0
”0” is read.
―
4
4
R
0
3
3
2
2
RMC
IDLE
mode
0:
Disabled
1:
Enabled
I2RMC
R/W
1
1
0
in
TMPM330
RMC
operation
0:
Disabled
1:
Enabled
Receptio
n
0:
Disabled
1:
Enabled
RMCREN
RMCEN
R/W
R/W
0
0
0
0
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