TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 214

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11 Serial Channel (SIO)
11.3.16 Direction of Data Transfer
11.3.17 Stop Bit Length
11.3.18 Status Flag
In the I/O interface mode, the direction of data transfer can be switched between “MSB first”
and “LSB first” by the data transfer direction setting bit <DRCHG> of the SC0MOD2 serial
mode control register 2. Don't switch the direction when data is being transferred.
In the UART transmission mode, the stop bit length can be set to either 1 or 2 bits by bit 4
<SBLEN> of the SC0MOD2 register.
If the double buffer function is enabled (SC0MOD2 <WBUF> = “1”), the bit 6 flag <RBFLL>
of the SC0MOD2 register indicates the condition of receive buffer full. When one frame of
data has been received and transferred from buffer 1 to buffer 2, this bit is set to “1” to show
that buffer 2 is full (data is stored in buffer 2). When the receive buffer is read by
CPU/DMAC, it is cleared to “0.” If <WBUF> is set to “0,” this bit is insignificant and must not
be used as a status flag. When double buffering is enabled (SC0MOD2 <WBUF> = “1”), the
bit 7 flag <TBEMP> of the SC0MOD2 register indicates that Transmit Buffer 2 is empty.
When data is moved from Transmit Buffer 2 to Transmit Buffer 1 (shift register), this bit is set
to “1” indicating that Transmit Buffer 2 is now empty. When data is set to the transmit buffer
by CPU/DMAC, the bit is cleared to “0.” If <WBUF> is set to “0,” this bit is insignificant and
must not be used as a status flag.
3. Framing error <FERR>: Bit 2 of the SC0CR register
In the UART mode, this bit is set to “1” when a framing error is generated. This flag is
set to “0” when it is read. A framing error is generated if the corresponding stop bit is
determined to be “0” by sampling the bit at around the center. Regardless of the
<SBLEN> (stop bit length) setting of the serial mode control register 2, SC0MOD2, the
stop bit status is determined by only 1 bit on the receive side.
Operation mode
UART
I/O Interface
(SCLK input)
I/O Interface
(SCLK output)
Under development
Error flag
OERR
PERR
FERR
OERR
PERR
FERR
OERR
PERR
FERR
Page202
Function
Fixed to 0 (WBUF = 0)
Fixed to 0
Operation undefined
Operation undefined
Fixed to 0
Overrun error flag
Parity error flag
Framing error flag
Overrun error flag
Underrun error flag (WBUF = 1)
TMPM330