TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 54

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7 Clock/Mode Control
7.3.5
7.3.6
(Note)
(Note 1)
(Note 2)
dividable.
to be input to each prescaler, the "fperiph" clock specified in the SYSCR1<FPSEL> can be divided
according to the setting in the SYSCR1<PRCK2:0>. After the controller is reset, fperiph/1 is selected as
φT0.
from X1 and
Input freq.
The TMPM330 offers two selectable system clocks: low-speed or high-speed. The high-speed clock is
Each peripheral function (TMRB0-9 and SIO0-2) has a prescaler for dividing a clock. As the clock φT0
10MHz
8MHz
X2
* PLL=ON/OFF setting: available in OSCCR0<PLLON>
•
•
•
•
Clock gear setting: available in SYSCR0<GEAR2:0>
System Clock
Prescaler Clock Control
To use the clock gear, ensure that you make the time setting such that prescaler output
φTn from each peripheral function is slower than fsys (φTn < fsys). Do not switch the
clock gear while the timer counter or other peripheral function is operating.
Switching of clock gear is executed when a value is written to the SYSCR0<GEAR2:0>
register. The actual switching takes place after a slight delay.
The CEC function uses the low-speed clock as a sampling clock. The allowable margin of
error when the CEC function is used is approximately ±4% at 32.768 kHz.
Input frequency from X1 and X2: 8MHz~10MH
Allows for oscillator connection or external clock input.
Clock gear:1/1, 1/2, 1/4, 1/8 (after reset: 1/1)
Input frequency from XT1 and XT2
Input Frequency Range Maximum Operating
operating
1MHz
30 ~ 34(kHz)
freq.
Min.
Table 7-3Range of High-frequency
Table 7-4Range of Low Frequency
operating
40MHz
Max.
freq.
Under development
Page42
Frequency
(PLL=OFF,
After reset
CG=1/1)
34 kHz
10
8
1/1
32
40
Clock gear (CG)
Minimum Operating
@PLL=ON
1/2
16
20
Frequency
30 kHz
1/4
10
8
1/8
4
5
1/1
10
8
Clock gear (CG)
@PLL=OFF
1/2
4
5
TMPM330
1/4
2.5
2
1.25
1/8
1