TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 310

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13 Consumer Electronics Control (CEC)
13.3.1.8 Detecting Error Interrupt
13.3.1.9 Details of Receive Error
(1)
(2)
bit. The received data is discarded.
waveform error), continue reception and send the reversed ACK response.
to the interrupt.
period does not comply with the specified minimum or maximum value, a cycle error interrupt is
generated.
bits. A cycle error can be detected for each sampling clock cycle between the ranges of -4 to +3
cycles from the minimum value (approx. 2.05 ms) or the maximum value (approx. 2.75 ms) defined
by the CEC standard.
generated.
interrupt or a minimum cycle error interrupt.
interrupt sets the CECRSTAT <CECRIMIN> bit.
is “0”, an ACK collision interrupt is generated. If it is “1”, and “0” is detected during the detection
period, the minimum cycle error interrupt is generated. The minimum cycle error causes CEC to
output “0” for approx. 3.6 ms.
ms from the starting point (the falling edge) of the ACK bit.
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start
It is possible to suspend a receive error interrupt (maximum cycle error, receive buffer overrun and
You can check the interrupt factor by monitoring the bit of the CECRSTAT register corresponding
Period between the falling edges of the two sequential bits is measured during reception. If the
The maximum and minimum cycles are specified in the CECRCR1 <CECMIN2:0> <CECMAX2:0>
The CECRSTAT <CECRIMIN> bit or the <CECRIMAX> bit is set if a cycle error interrupt is
The minimum cycle error causes CEC to output “0” for approx. 3.6 ms.
At an ACK response, detecting “0” after the specified period to output generates an ACK collision
The ACK collision interrupt sets the CECRSTAT <CECRIACK> bit. The minimum cycle error
The following describes the period and method of detection.
Detection starts approx. 0.3 ms after the end of the period of outputting “0” and ends approx 2.0
At 0.3 ms from the end of the period of outputting “0”, CEC checks if the CEC line is “0” or not. If it
Cycle Error
ACK Collision
Under development
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TMPM330