TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 218

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11 Serial Channel (SIO)
SC0CR
11.4.3
<RB8>:
<EVEN>:
<PE>:
<OERR>:
<PERR>:
<FERR>:
<SCLKS>:
<IOC>:
(Note)
bit Symbol
Read/Write
After reset
Control register
Function
Any error flag is cleared when read.
“0”: odd parity.
“1”: even parity.
The parity bit may be used only in the 7- or 8-bit UART mode.
The parity bit may be used only in the 7- or 8-bit UART mode.
“0”: baud rate generator
Selects even or odd parity.
Controls enabling/ disabling parity.
Error flag
Indicate overrun error, parity error, underrun error and framing error.
Selects input clock in the I/O interface mode.
9
“1”: SCLK0 pin input.
Selects edge for data transmission and reception.
“0”:
“1”:
th
bit of the received data in the 9 bits UART mode.
Data transmit/receive at rising edges of SCLK0
Data transmit/receive at falling edges of SCLK0
Receive
data bit 8
(For
UART)
RB8
7
R
0
(see note)
Parity
(For
UART)
0: Odd
1: Even
EVEN
6
0
R/W
Add parity
(For
UART)
0:
Disabled
1: Enabled
Under development
PE
5
0
Page206
Overrun
OERR
R (Cleared to “0” when read)
4
0
0: Normal operation
Parity/
underrun
1: Error
PERR
3
0
Framing
FERR
2
0
0: SCLK0
1: SCLK0
SCLKS
1
0
R/W
(For
0: Baud
1: SCLK0
interfac
e)
rate
generato
r
pin input
IOC
TMPM330
0
0
I/O