TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 83

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8.5.2.3
8.5.2.4
8.5.2.5
according to the active level specified in the clock generator, and is notified to the CPU.
level-sensitive interrupt request must be held at the active level until it is detected, otherwise the
interrupt request will cease to exist when the signal level changes from active to inactive.
“H” level to the CPU until the interrupt request is cleared in the CG Interrupt Request Clear
(ICRCG) Register. If a standby mode is exited without clearing the interrupt request, the same
interrupt will be detected again when normal operation is resumed. Be sure to clear each interrupt
request in the ISR.
stack before entering the ISR.
If an interrupt source is used for clearing a standby mode, an interrupt request is detected
An edge-triggered interrupt request, once detected, is held in the clock generator. A
When the clock generator detects an interrupt request, it keeps sending the interrupt signal in
The CPU detects an interrupt request with the highest priority.
On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the
CPU processing
Detection by Clock Generator
Detection by CPU
Under development
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TMPM330